Author: Armin Rigo <ar...@tunes.org>
Branch:
Changeset: r48623:21b6ffe463ac
Date: 2011-10-31 17:38 +0100
http://bitbucket.org/pypy/pypy/changeset/21b6ffe463ac/
Log: Test and fix.
diff --git a/pypy/jit/backend/x86/assembler.py
b/pypy/jit/backend/x86/assembler.py
--- a/pypy/jit/backend/x86/assembler.py
+++ b/pypy/jit/backend/x86/assembler.py
@@ -1605,6 +1605,7 @@
# XXX should not use IMUL in most cases
assert isinstance(temp_loc, RegLoc)
assert isinstance(index_loc, RegLoc)
+ assert not temp_loc.is_xmm
self.mc.IMUL_rri(temp_loc.value, index_loc.value,
itemsize_loc.value)
assert isinstance(ofs_loc, ImmedLoc)
@@ -1612,8 +1613,8 @@
def genop_getinteriorfield_gc(self, op, arglocs, resloc):
(base_loc, ofs_loc, itemsize_loc, fieldsize_loc,
- index_loc, sign_loc) = arglocs
- src_addr = self._get_interiorfield_addr(resloc, index_loc,
+ index_loc, temp_loc, sign_loc) = arglocs
+ src_addr = self._get_interiorfield_addr(temp_loc, index_loc,
itemsize_loc, base_loc,
ofs_loc)
self.load_from_mem(resloc, src_addr, fieldsize_loc, sign_loc)
diff --git a/pypy/jit/backend/x86/regalloc.py b/pypy/jit/backend/x86/regalloc.py
--- a/pypy/jit/backend/x86/regalloc.py
+++ b/pypy/jit/backend/x86/regalloc.py
@@ -1143,9 +1143,20 @@
# 'index' but must be in a different register than 'base'.
self.rm.possibly_free_var(op.getarg(1))
result_loc = self.force_allocate_reg(op.result, [op.getarg(0)])
+ assert isinstance(result_loc, RegLoc)
+ # two cases: 1) if result_loc is a normal register, use it as temp_loc
+ if not result_loc.is_xmm:
+ temp_loc = result_loc
+ else:
+ # 2) if result_loc is an xmm register, we (likely) need another
+ # temp_loc that is a normal register. It can be in the same
+ # register as 'index' but not 'base'.
+ tempvar = TempBox()
+ temp_loc = self.rm.force_allocate_reg(tempvar, [op.getarg(0)])
+ self.rm.possibly_free_var(tempvar)
self.rm.possibly_free_var(op.getarg(0))
self.Perform(op, [base_loc, ofs, itemsize, fieldsize,
- index_loc, sign_loc], result_loc)
+ index_loc, temp_loc, sign_loc], result_loc)
def consider_int_is_true(self, op, guard_op):
# doesn't need arg to be in a register
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