[pypy-commit] pypy ppc-jit-backend: Optimize zero-extend and sign-extend in _ensure_result_bit_extension

[edelsohn]

Author: edelsohn
Branch: ppc-jit-backend
Changeset: r48651:058e97bccb87
Date: 2011-11-01 15:16 -0400
http://bitbucket.org/pypy/pypy/changeset/058e97bccb87/

Log:    Optimize zero-extend and sign-extend in _ensure_result_bit_extension
        and add PPC64 support.

diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py 
b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
@@ -666,25 +666,30 @@
         assert 0, "not supported location"
 
     def _ensure_result_bit_extension(self, resloc, size, signed):
-        if size == 4:
-            return
         if size == 1:
             if not signed: #unsigned char
-                self.mc.load_imm(r.r0, 0xFF)
-                self.mc.and_(resloc.value, resloc.value, r.r0.value)
+                if IS_PPC32:
+                    self.mc.load_imm(r.r0, 0xFF)
+                    self.mc.and_(resloc.value, resloc.value, r.r0.value)
+                else:
+                    self.mc.rldicl(resloc.value, resloc.value, 0, 56)
             else:
-                self.mc.load_imm(r.r0, 24)
-                self.mc.slw(resloc.value, resloc.value, r.r0.value)
-                self.mc.sraw(resloc.value, resloc.value, r.r0.value)
+                self.mc.extsb(resloc.value, resloc.value)
         elif size == 2:
             if not signed:
-                self.mc.load_imm(r.r0, 16)
-                self.mc.slw(resloc.value, resloc.value, r.r0.value)
-                self.mc.srw(resloc.value, resloc.value, r.r0.value)
+                if IS_PPC_32:
+                    self.mc.load_imm(r.r0, 16)
+                    self.mc.slw(resloc.value, resloc.value, r.r0.value)
+                    self.mc.srw(resloc.value, resloc.value, r.r0.value)
+                else:
+                    self.mc.rldicl(resloc.value, resloc.value, 0, 48)
             else:
-                self.mc.load_imm(r.r0, 16)
-                self.mc.slw(resloc.value, resloc.value, r.r0.value)
-                self.mc.sraw(resloc.value, resloc.value, r.r0.value)
+                self.mc.extsh(resloc.value, resloc.value)
+        elif size == 4:
+            if not signed:
+                self.mc.rldicl(resloc.value, resloc.value, 0, 32)
+            else:
+                self.mc.extsw(resloc.value, resloc.value)
 
     def mark_gc_roots(self, force_index, use_copy_area=False):
         if force_index < 0:
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