Author: hager <sven.ha...@uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r49309:ce80006b9449
Date: 2011-11-11 06:41 -0800
http://bitbucket.org/pypy/pypy/changeset/ce80006b9449/
Log: (bivab, hager): Code refactorings and debugging in int operations
diff --git a/pypy/jit/backend/ppc/ppcgen/codebuilder.py
b/pypy/jit/backend/ppc/ppcgen/codebuilder.py
--- a/pypy/jit/backend/ppc/ppcgen/codebuilder.py
+++ b/pypy/jit/backend/ppc/ppcgen/codebuilder.py
@@ -1018,6 +1018,39 @@
def copy_to_raw_memory(self, addr):
self._copy_to_raw_memory(addr)
+ def cmp_op(self, block, a, b, imm=False, signed=True):
+ if IS_PPC_32:
+ if signed:
+ if imm:
+ # 32 bit immediate signed
+ self.cmpwi(block, a, b)
+ else:
+ # 32 bit signed
+ self.cmpw(block, a, b)
+ else:
+ if imm:
+ # 32 bit immediate unsigned
+ self.cmplwi(block, a, b)
+ else:
+ # 32 bit unsigned
+ self.cmplw(block, a, b)
+ else:
+ if signed:
+ if imm:
+ # 64 bit immediate signed
+ self.cmpdi(block, a, b)
+ else:
+ # 64 bit signed
+ self.cmpd(block, a, b)
+ else:
+ if imm:
+ # 64 bit immediate unsigned
+ self.cmpldi(block, a, b)
+ else:
+ # 64 bit unsigned
+ self.cmpld(block, a, b)
+
+
class BranchUpdater(PPCAssembler):
def __init__(self):
PPCAssembler.__init__(self)
diff --git a/pypy/jit/backend/ppc/ppcgen/helper/assembler.py
b/pypy/jit/backend/ppc/ppcgen/helper/assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/helper/assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/helper/assembler.py
@@ -8,57 +8,24 @@
def f(self, op, arglocs, regalloc):
l0, l1, res = arglocs
# do the comparison
- if signed:
- if l1.is_imm():
- if IS_PPC_32:
- self.mc.cmpwi(0, l0.value, l1.value)
- else:
- self.mc.cmpdi(0, l0.value, l1.value)
- else:
- if IS_PPC_32:
- self.mc.cmpw(0, l0.value, l1.value)
- else:
- self.mc.cmpd(0, l0.value, l1.value)
-
- # After the comparison, place the result
- # in the first bit of the CR
- if condition == c.LT:
- self.mc.cror(0, 0, 0)
- elif condition == c.LE:
- self.mc.cror(0, 0, 2)
- elif condition == c.EQ:
- self.mc.cror(0, 2, 2)
- elif condition == c.GE:
- self.mc.cror(0, 1, 2)
- elif condition == c.GT:
- self.mc.cror(0, 1, 1)
- elif condition == c.NE:
- self.mc.cror(0, 0, 1)
- else:
- assert 0, "condition not known"
-
+ self.mc.cmp_op(0, l0.value, l1.value,
+ imm=l1.is_imm(), signed=signed)
+ # After the comparison, place the result
+ # in the first bit of the CR
+ if condition == c.LT or condition == c.U_LT:
+ self.mc.cror(0, 0, 0)
+ elif condition == c.LE or condition == c.U_LE:
+ self.mc.cror(0, 0, 2)
+ elif condition == c.EQ:
+ self.mc.cror(0, 2, 2)
+ elif condition == c.GE or condition == c.U_GE:
+ self.mc.cror(0, 1, 2)
+ elif condition == c.GT or condition == c.U_GT:
+ self.mc.cror(0, 1, 1)
+ elif condition == c.NE:
+ self.mc.cror(0, 0, 1)
else:
- if l1.is_imm():
- if IS_PPC_32:
- self.mc.cmplwi(0, l0.value, l1.value)
- else:
- self.mc.cmpldi(0, l0.value, l1.value)
- else:
- if IS_PPC_32:
- self.mc.cmplw(0, l0.value, l1.value)
- else:
- self.mc.cmpld(0, l0.value, l1.value)
-
- if condition == c.U_LT:
- self.mc.cror(0, 0, 0)
- elif condition == c.U_LE:
- self.mc.cror(0, 0, 2)
- elif condition == c.U_GT:
- self.mc.cror(0, 1, 1)
- elif condition == c.U_GE:
- self.mc.cror(0, 1, 2)
- else:
- assert 0, "condition not known"
+ assert 0, "condition not known"
resval = res.value
# move the content of the CR to resval
@@ -71,7 +38,7 @@
def f(self, op, arglocs, regalloc):
reg, res = arglocs
- self.mc.cmpwi(0, reg.value, 0)
+ self.mc.cmp_op(0, reg.value, 0, imm=True)
if condition == c.IS_ZERO:
self.mc.cror(0, 2, 2)
elif condition == c.IS_TRUE:
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