Author: David Schneider <[email protected]>
Branch: arm-backend-2
Changeset: r49970:d61888e925b8
Date: 2011-11-29 14:01 +0100
http://bitbucket.org/pypy/pypy/changeset/d61888e925b8/
Log: refactor check_imm_arg
diff --git a/pypy/jit/backend/arm/assembler.py
b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -9,7 +9,7 @@
from pypy.jit.backend.arm.arch import WORD, FUNC_ALIGN, PC_OFFSET,
N_REGISTERS_SAVED_BY_MALLOC
from pypy.jit.backend.arm.codebuilder import ARMv7Builder, OverwritingBuilder
from pypy.jit.backend.arm.regalloc import (Regalloc, ARMFrameManager,
ARMv7RegisterMananger,
- _check_imm_arg, TempInt,
+ check_imm_arg, TempInt,
TempPtr,
operations as regalloc_operations,
operations_with_guard as
regalloc_operations_with_guard)
@@ -245,7 +245,8 @@
i += 4
if group == self.FLOAT_TYPE:
value = decode64(stack, frame_depth - stack_loc*WORD)
- self.fail_boxes_float.setitem(fail_index, value)
+ fvalue = longlong2float(value)
+ self.fail_boxes_float.setitem(fail_index, fvalue)
continue
else:
value = decode32(stack, frame_depth - stack_loc*WORD)
@@ -914,14 +915,14 @@
temp = r.lr
else:
temp = r.ip
- offset = ConstInt(loc.position*WORD)
- if not _check_imm_arg(offset, size=0xFFF):
+ offset = loc.position*WORD
+ if not check_imm_arg(offset, size=0xFFF):
self.mc.PUSH([temp.value], cond=cond)
- self.mc.gen_load_int(temp.value, -offset.value, cond=cond)
+ self.mc.gen_load_int(temp.value, -offset, cond=cond)
self.mc.STR_rr(prev_loc.value, r.fp.value, temp.value,
cond=cond)
self.mc.POP([temp.value], cond=cond)
else:
- self.mc.STR_ri(prev_loc.value, r.fp.value,
imm=-1*offset.value, cond=cond)
+ self.mc.STR_ri(prev_loc.value, r.fp.value, imm=-offset,
cond=cond)
else:
assert 0, 'unsupported case'
@@ -931,27 +932,27 @@
assert prev_loc.type != FLOAT, 'trying to load from an
incompatible location into a core register'
assert loc is not r.lr, 'lr is not supported as a target when
moving from the stack'
# unspill a core register
- offset = ConstInt(prev_loc.position*WORD)
- if not _check_imm_arg(offset, size=0xFFF):
+ offset = prev_loc.position*WORD
+ if not check_imm_arg(offset, size=0xFFF):
self.mc.PUSH([r.lr.value], cond=cond)
pushed = True
- self.mc.gen_load_int(r.lr.value, -offset.value, cond=cond)
+ self.mc.gen_load_int(r.lr.value, -offset, cond=cond)
self.mc.LDR_rr(loc.value, r.fp.value, r.lr.value, cond=cond)
else:
- self.mc.LDR_ri(loc.value, r.fp.value, imm=-offset.value,
cond=cond)
+ self.mc.LDR_ri(loc.value, r.fp.value, imm=-offset, cond=cond)
if pushed:
self.mc.POP([r.lr.value], cond=cond)
elif loc.is_vfp_reg():
assert prev_loc.type == FLOAT, 'trying to load from an
incompatible location into a float register'
# load spilled value into vfp reg
- offset = ConstInt(prev_loc.position*WORD)
+ offset = prev_loc.position*WORD
self.mc.PUSH([r.ip.value], cond=cond)
pushed = True
- if not _check_imm_arg(offset):
- self.mc.gen_load_int(r.ip.value, offset.value, cond=cond)
+ if not check_imm_arg(offset):
+ self.mc.gen_load_int(r.ip.value, offset, cond=cond)
self.mc.SUB_rr(r.ip.value, r.fp.value, r.ip.value, cond=cond)
else:
- self.mc.SUB_ri(r.ip.value, r.fp.value, offset.value, cond=cond)
+ self.mc.SUB_ri(r.ip.value, r.fp.value, offset, cond=cond)
self.mc.VLDR(loc.value, r.ip.value, cond=cond)
if pushed:
self.mc.POP([r.ip.value], cond=cond)
@@ -973,12 +974,12 @@
assert loc.type == FLOAT, 'trying to store to an incompatible
location from a float register'
# spill vfp register
self.mc.PUSH([r.ip.value], cond=cond)
- offset = ConstInt(loc.position*WORD)
- if not _check_imm_arg(offset):
- self.mc.gen_load_int(r.ip.value, offset.value, cond=cond)
+ offset = loc.position*WORD
+ if not check_imm_arg(offset):
+ self.mc.gen_load_int(r.ip.value, offset, cond=cond)
self.mc.SUB_rr(r.ip.value, r.fp.value, r.ip.value, cond=cond)
else:
- self.mc.SUB_ri(r.ip.value, r.fp.value, offset.value, cond=cond)
+ self.mc.SUB_ri(r.ip.value, r.fp.value, offset, cond=cond)
self.mc.VSTR(prev_loc.value, r.ip.value, cond=cond)
self.mc.POP([r.ip.value], cond=cond)
else:
@@ -1016,17 +1017,17 @@
self.mc.POP([r.ip.value], cond=cond)
elif vfp_loc.is_stack() and vfp_loc.type == FLOAT:
# load spilled vfp value into two core registers
- offset = ConstInt((vfp_loc.position)*WORD)
- if not _check_imm_arg(offset, size=0xFFF):
+ offset = vfp_loc.position*WORD
+ if not check_imm_arg(offset, size=0xFFF):
self.mc.PUSH([r.ip.value], cond=cond)
- self.mc.gen_load_int(r.ip.value, -offset.value, cond=cond)
+ self.mc.gen_load_int(r.ip.value, -offset, cond=cond)
self.mc.LDR_rr(reg1.value, r.fp.value, r.ip.value, cond=cond)
self.mc.ADD_ri(r.ip.value, r.ip.value, imm=WORD, cond=cond)
self.mc.LDR_rr(reg2.value, r.fp.value, r.ip.value, cond=cond)
self.mc.POP([r.ip.value], cond=cond)
else:
- self.mc.LDR_ri(reg1.value, r.fp.value, imm=-offset.value,
cond=cond)
- self.mc.LDR_ri(reg2.value, r.fp.value, imm=-offset.value+WORD,
cond=cond)
+ self.mc.LDR_ri(reg1.value, r.fp.value, imm=-offset, cond=cond)
+ self.mc.LDR_ri(reg2.value, r.fp.value, imm=-offset+WORD,
cond=cond)
else:
assert 0, 'unsupported case'
@@ -1038,17 +1039,17 @@
self.mc.VMOV_cr(vfp_loc.value, reg1.value, reg2.value, cond=cond)
elif vfp_loc.is_stack():
# move from two core registers to a float stack location
- offset = ConstInt((vfp_loc.position)*WORD)
- if not _check_imm_arg(offset, size=0xFFF):
+ offset = vfp_loc.position*WORD
+ if not check_imm_arg(offset, size=0xFFF):
self.mc.PUSH([r.ip.value], cond=cond)
- self.mc.gen_load_int(r.ip.value, -offset.value, cond=cond)
+ self.mc.gen_load_int(r.ip.value, -offset, cond=cond)
self.mc.STR_rr(reg1.value, r.fp.value, r.ip.value, cond=cond)
self.mc.ADD_ri(r.ip.value, r.ip.value, imm=WORD, cond=cond)
self.mc.STR_rr(reg2.value, r.fp.value, r.ip.value, cond=cond)
self.mc.POP([r.ip.value], cond=cond)
else:
- self.mc.STR_ri(reg1.value, r.fp.value, imm=-offset.value,
cond=cond)
- self.mc.STR_ri(reg2.value, r.fp.value, imm=-offset.value+WORD,
cond=cond)
+ self.mc.STR_ri(reg1.value, r.fp.value, imm=-offset, cond=cond)
+ self.mc.STR_ri(reg2.value, r.fp.value, imm=-offset+WORD,
cond=cond)
else:
assert 0, 'unsupported case'
@@ -1106,7 +1107,7 @@
self.mc.gen_load_int(r.r0.value, nursery_free_adr)
self.mc.LDR_ri(r.r0.value, r.r0.value)
- if _check_imm_arg(ConstInt(size)):
+ if check_imm_arg(size):
self.mc.ADD_ri(r.r1.value, r.r0.value, size)
else:
self.mc.gen_load_int(r.r1.value, size)
diff --git a/pypy/jit/backend/arm/helper/regalloc.py
b/pypy/jit/backend/arm/helper/regalloc.py
--- a/pypy/jit/backend/arm/helper/regalloc.py
+++ b/pypy/jit/backend/arm/helper/regalloc.py
@@ -3,26 +3,34 @@
from pypy.jit.backend.arm.codebuilder import AbstractARMv7Builder
from pypy.jit.metainterp.history import ConstInt, BoxInt, Box, FLOAT
from pypy.jit.metainterp.history import ConstInt
+from pypy.rlib.objectmodel import we_are_translated
-# XXX create a version that does not need a ConstInt
-def _check_imm_arg(arg, size=0xFF, allow_zero=True):
+def check_imm_arg(arg, size=0xFF, allow_zero=True):
+ assert not isinstance(arg, ConstInt)
+ if not we_are_translated():
+ if not isinstance(arg, int):
+ import pdb; pdb.set_trace()
+ i = arg
+ if allow_zero:
+ lower_bound = i >= 0
+ else:
+ lower_bound = i > 0
+ return i <= size and lower_bound
+
+def check_imm_box(arg, size=0xFF, allow_zero=True):
if isinstance(arg, ConstInt):
- i = arg.getint()
- if allow_zero:
- lower_bound = i >= 0
- else:
- lower_bound = i > 0
- return i <= size and lower_bound
+ return check_imm_arg(arg.getint(), size, allow_zero)
return False
+
def prepare_op_ri(name=None, imm_size=0xFF, commutative=True, allow_zero=True):
def f(self, op, fcond):
assert fcond is not None
a0 = op.getarg(0)
a1 = op.getarg(1)
boxes = list(op.getarglist())
- imm_a0 = _check_imm_arg(a0, imm_size, allow_zero=allow_zero)
- imm_a1 = _check_imm_arg(a1, imm_size, allow_zero=allow_zero)
+ imm_a0 = check_imm_box(a0, imm_size, allow_zero=allow_zero)
+ imm_a1 = check_imm_box(a1, imm_size, allow_zero=allow_zero)
if not imm_a0 and imm_a1:
l0 = self._ensure_value_is_boxed(a0)
l1 = self.make_sure_var_in_reg(a1, boxes)
@@ -101,7 +109,7 @@
assert fcond is not None
boxes = list(op.getarglist())
arg0, arg1 = boxes
- imm_a1 = _check_imm_arg(arg1)
+ imm_a1 = check_imm_box(arg1)
l0 = self._ensure_value_is_boxed(arg0, forbidden_vars=boxes)
if imm_a1:
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -8,7 +8,9 @@
prepare_op_ri,
prepare_cmp_op,
prepare_float_op,
- _check_imm_arg)
+ check_imm_arg,
+ check_imm_box
+ )
from pypy.jit.backend.arm.jump import remap_frame_layout_mixed
from pypy.jit.backend.arm.arch import MY_COPY_OF_REGS, WORD
from pypy.jit.codewriter import longlong
@@ -102,7 +104,8 @@
assert type == FLOAT # for now
box = TempFloat()
self.temp_boxes.append(box)
- return self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
selected_reg=selected_reg)
+ reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
selected_reg=selected_reg)
+ return reg
class ARMv7RegisterMananger(RegisterManager):
@@ -135,6 +138,7 @@
else:
assert isinstance(c, ConstPtr)
return locations.ImmLocation(rffi.cast(lltype.Signed, c.value))
+ assert 0
def ensure_value_is_boxed(self, thing, forbidden_vars=None):
box = None
@@ -156,7 +160,8 @@
assert type == INT or type == REF
box = TempBox()
self.temp_boxes.append(box)
- return self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
selected_reg=selected_reg)
+ reg = self.force_allocate_reg(box, forbidden_vars=forbidden_vars,
selected_reg=selected_reg)
+ return reg
class Regalloc(object):
@@ -335,8 +340,8 @@
def _prepare_op_int_add(self, op, fcond):
boxes = list(op.getarglist())
a0, a1 = boxes
- imm_a0 = _check_imm_arg(a0)
- imm_a1 = _check_imm_arg(a1)
+ imm_a0 = check_imm_box(a0)
+ imm_a1 = check_imm_box(a1)
if not imm_a0 and imm_a1:
l0 = self._ensure_value_is_boxed(a0)
l1 = self.make_sure_var_in_reg(a1, boxes)
@@ -357,8 +362,8 @@
def _prepare_op_int_sub(self, op, fcond):
a0, a1 = boxes = op.getarglist()
- imm_a0 = _check_imm_arg(a0)
- imm_a1 = _check_imm_arg(a1)
+ imm_a0 = check_imm_box(a0)
+ imm_a1 = check_imm_box(a1)
if not imm_a0 and imm_a1:
l0 = self._ensure_value_is_boxed(a0, boxes)
l1 = self.make_sure_var_in_reg(a1, boxes)
@@ -517,7 +522,7 @@
def prepare_op_guard_value(self, op, fcond):
boxes = list(op.getarglist())
a0, a1 = boxes
- imm_a1 = _check_imm_arg(a1)
+ imm_a1 = check_imm_box(a1)
l0 = self._ensure_value_is_boxed(a0, boxes)
if not imm_a1:
l1 = self._ensure_value_is_boxed(a1, boxes)
@@ -616,11 +621,11 @@
ofs, size, ptr = self._unpack_fielddescr(op.getdescr())
base_loc = self._ensure_value_is_boxed(a0, boxes)
value_loc = self._ensure_value_is_boxed(a1, boxes)
- c_ofs = ConstInt(ofs)
- if _check_imm_arg(c_ofs):
+ if check_imm_arg(ofs):
ofs_loc = imm(ofs)
else:
- ofs_loc = self._ensure_value_is_boxed(c_ofs, boxes)
+ ofs_loc = self.get_scratch_reg(INT, boxes)
+ self.assembler.load(ofs_loc, imm(ofs))
return [value_loc, base_loc, ofs_loc, imm(size)]
prepare_op_setfield_raw = prepare_op_setfield_gc
@@ -629,11 +634,12 @@
a0 = op.getarg(0)
ofs, size, ptr = self._unpack_fielddescr(op.getdescr())
base_loc = self._ensure_value_is_boxed(a0)
- c_ofs = ConstInt(ofs)
- if _check_imm_arg(c_ofs):
- ofs_loc = imm(ofs)
+ immofs = imm(ofs)
+ if check_imm_arg(ofs):
+ ofs_loc = immofs
else:
- ofs_loc = self._ensure_value_is_boxed(c_ofs)
+ ofs_loc = self.get_scratch_reg(INT, [a0])
+ self.assembler.load(ofs_loc, immofs)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
res = self.force_allocate_reg(op.result)
@@ -649,11 +655,12 @@
args = op.getarglist()
base_loc = self._ensure_value_is_boxed(op.getarg(0), args)
index_loc = self._ensure_value_is_boxed(op.getarg(1), args)
- c_ofs = ConstInt(ofs)
- if _check_imm_arg(c_ofs):
- ofs_loc = imm(ofs)
+ immofs = imm(ofs)
+ if check_imm_arg(ofs):
+ ofs_loc = immofs
else:
- ofs_loc = self._ensure_value_is_boxed(c_ofs, args)
+ ofs_loc = self.get_scratch_reg(INT, args)
+ self.assembler.load(ofs_loc, immofs)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
result_loc = self.force_allocate_reg(op.result)
@@ -668,11 +675,12 @@
base_loc = self._ensure_value_is_boxed(op.getarg(0), args)
index_loc = self._ensure_value_is_boxed(op.getarg(1), args)
value_loc = self._ensure_value_is_boxed(op.getarg(2), args)
- c_ofs = ConstInt(ofs)
- if _check_imm_arg(c_ofs):
- ofs_loc = imm(ofs)
+ immofs = imm(ofs)
+ if check_imm_arg(ofs):
+ ofs_loc = immofs
else:
- ofs_loc = self._ensure_value_is_boxed(c_ofs, op.getarglist())
+ ofs_loc = self.get_scratch_reg(INT, args)
+ self.assembler.load(ofs_loc, immofs)
return [base_loc, index_loc, value_loc, ofs_loc, imm(ofs),
imm(itemsize), imm(fieldsize)]
@@ -695,7 +703,7 @@
base_loc = self._ensure_value_is_boxed(a0, args)
ofs_loc = self._ensure_value_is_boxed(a1, args)
value_loc = self._ensure_value_is_boxed(a2, args)
- assert _check_imm_arg(ConstInt(base_ofs))
+ assert check_imm_arg(base_ofs)
return [value_loc, base_loc, ofs_loc, imm(scale), imm(base_ofs)]
prepare_op_setarrayitem_raw = prepare_op_setarrayitem_gc
@@ -708,7 +716,7 @@
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
res = self.force_allocate_reg(op.result)
- assert _check_imm_arg(ConstInt(base_ofs))
+ assert check_imm_arg(base_ofs)
return [res, base_loc, ofs_loc, imm(scale), imm(base_ofs)]
prepare_op_getarrayitem_raw = prepare_op_getarrayitem_gc
@@ -719,13 +727,12 @@
l0 = self._ensure_value_is_boxed(op.getarg(0))
basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
self.cpu.translate_support_code)
- ofs_box = ConstInt(ofs_length)
- imm_ofs = _check_imm_arg(ofs_box)
-
- if imm_ofs:
- l1 = self.make_sure_var_in_reg(ofs_box, args)
+ immofs = imm(ofs_length)
+ if check_imm_arg(ofs_length):
+ l1 = immofs
else:
- l1 = self._ensure_value_is_boxed(ofs_box, args)
+ l1 = self.get_scratch_reg(INT, args)
+ self.assembler.load(l1, immofs)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
@@ -739,7 +746,7 @@
base_loc = self._ensure_value_is_boxed(boxes[0])
a1 = boxes[1]
- imm_a1 = _check_imm_arg(a1)
+ imm_a1 = check_imm_box(a1)
if imm_a1:
ofs_loc = self.make_sure_var_in_reg(a1, boxes)
else:
@@ -771,13 +778,12 @@
l0 = self._ensure_value_is_boxed(op.getarg(0))
basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
self.cpu.translate_support_code)
- ofs_box = ConstInt(ofs_length)
- imm_ofs = _check_imm_arg(ofs_box)
-
- if imm_ofs:
- l1 = imm(ofs_length)
+ immofs = imm(ofs_length)
+ if check_imm_arg(ofs_length):
+ l1 = immofs
else:
- l1 = self._ensure_value_is_boxed(ofs_box)
+ l1 = self.get_scratch_reg(INT, [op.getarg(0)])
+ self.assembler.load(l1, immofs)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
@@ -810,7 +816,7 @@
def prepare_op_same_as(self, op, fcond):
arg = op.getarg(0)
- imm_arg = _check_imm_arg(arg)
+ imm_arg = check_imm_box(arg)
if imm_arg:
argloc = self.make_sure_var_in_reg(arg)
else:
@@ -952,14 +958,17 @@
v = op.getarg(0)
res_v = op.result
boxes = [v, res_v]
- itemsize_box = ConstInt(itemsize)
- ofs_items_box = ConstInt(ofs_items)
- if _check_imm_arg(ofs_items_box):
- ofs_items_loc = self.convert_to_imm(ofs_items_box)
+ immofs = imm(ofs_items)
+ if check_imm_arg(ofs_items):
+ ofs_items_loc = immofs
else:
- ofs_items_loc = self._ensure_value_is_boxed(ofs_items_box, boxes)
+ ofs_items_loc = self.get_scratch_reg(INT, boxes)
+ self.assembler.load(ofs_items_loc, immofs)
vloc = self._ensure_value_is_boxed(v, [res_v])
- size = self._ensure_value_is_boxed(itemsize_box, boxes)
+
+ size = self.get_scratch_reg(INT, boxes)
+ self.assembler.load(itemsize)
+
self.assembler._regalloc_malloc_varsize(size, size_box,
vloc, vbox, ofs_items_loc, self, res_v)
base_loc = self.make_sure_var_in_reg(res_v)
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