Author: Armin Rigo <[email protected]>
Branch:
Changeset: r56530:6f7ce5934a7b
Date: 2012-08-01 23:56 +0200
http://bitbucket.org/pypy/pypy/changeset/6f7ce5934a7b/
Log: Minor improvement maybe: replace "ADD reg, const" and "SUB reg,
const" with a LEA. The idea is that LEA is more flexible because it
can name a destination register != source register.
diff --git a/pypy/jit/backend/x86/assembler.py
b/pypy/jit/backend/x86/assembler.py
--- a/pypy/jit/backend/x86/assembler.py
+++ b/pypy/jit/backend/x86/assembler.py
@@ -998,6 +998,22 @@
getattr(self.mc, asmop)(arglocs[0], arglocs[1])
return genop_binary
+ def _binaryop_or_lea(asmop, is_add):
+ def genop_binary_or_lea(self, op, arglocs, result_loc):
+ if result_loc is arglocs[0]:
+ getattr(self.mc, asmop)(arglocs[0], arglocs[1])
+ else:
+ loc = arglocs[0]
+ argloc = arglocs[1]
+ assert isinstance(loc, RegLoc)
+ assert isinstance(argloc, ImmedLoc)
+ assert isinstance(result_loc, RegLoc)
+ delta = argloc.value
+ if not is_add: # subtraction
+ delta = -delta
+ self.mc.LEA_rm(result_loc.value, (loc.value, delta))
+ return genop_binary_or_lea
+
def _cmpop(cond, rev_cond):
def genop_cmp(self, op, arglocs, result_loc):
rl = result_loc.lowest8bits()
@@ -1224,8 +1240,8 @@
genop_int_neg = _unaryop("NEG")
genop_int_invert = _unaryop("NOT")
- genop_int_add = _binaryop("ADD", True)
- genop_int_sub = _binaryop("SUB")
+ genop_int_add = _binaryop_or_lea("ADD", True)
+ genop_int_sub = _binaryop_or_lea("SUB", False)
genop_int_mul = _binaryop("IMUL", True)
genop_int_and = _binaryop("AND", True)
genop_int_or = _binaryop("OR", True)
diff --git a/pypy/jit/backend/x86/regalloc.py b/pypy/jit/backend/x86/regalloc.py
--- a/pypy/jit/backend/x86/regalloc.py
+++ b/pypy/jit/backend/x86/regalloc.py
@@ -23,6 +23,7 @@
TempBox
from pypy.jit.backend.x86.arch import WORD, FRAME_FIXED_SIZE
from pypy.jit.backend.x86.arch import IS_X86_32, IS_X86_64, MY_COPY_OF_REGS
+from pypy.jit.backend.x86 import rx86
from pypy.rlib.rarithmetic import r_longlong
class X86RegisterManager(RegisterManager):
@@ -610,9 +611,33 @@
loc, argloc = self._consider_binop_part(op)
self.Perform(op, [loc, argloc], loc)
- consider_int_add = _consider_binop
+ def _consider_lea(self, op, loc):
+ argloc = self.loc(op.getarg(1))
+ self.rm.possibly_free_var(op.getarg(0))
+ resloc = self.force_allocate_reg(op.result)
+ self.Perform(op, [loc, argloc], resloc)
+
+ def _consider_binop_add(self, op):
+ loc = self.loc(op.getarg(0))
+ y = op.getarg(1)
+ if (isinstance(loc, RegLoc) and
+ isinstance(y, ConstInt) and rx86.fits_in_32bits(y.value)):
+ self._consider_lea(op, loc)
+ else:
+ self._consider_binop(op)
+
+ def _consider_binop_sub(self, op):
+ loc = self.loc(op.getarg(0))
+ y = op.getarg(1)
+ if (isinstance(loc, RegLoc) and
+ isinstance(y, ConstInt) and rx86.fits_in_32bits(-y.value)):
+ self._consider_lea(op, loc)
+ else:
+ self._consider_binop(op)
+
+ consider_int_add = _consider_binop_add
consider_int_mul = _consider_binop
- consider_int_sub = _consider_binop
+ consider_int_sub = _consider_binop_sub
consider_int_and = _consider_binop
consider_int_or = _consider_binop
consider_int_xor = _consider_binop
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