Author: Maciej Fijalkowski <[email protected]>
Branch: jitframe-on-heap
Changeset: r61183:71edf3e0a14f
Date: 2013-02-13 21:17 +0200
http://bitbucket.org/pypy/pypy/changeset/71edf3e0a14f/
Log: kill more duplication
diff --git a/rpython/jit/backend/arm/assembler.py
b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -734,26 +734,8 @@
return AsmInfo(ops_offset, startpos + rawstart, codeendpos - startpos)
- def rebuild_faillocs_from_descr(self, descr, inputargs):
- locs = []
- GPR_REGS = len(CoreRegisterManager.all_regs)
- VFP_REGS = len(VFPRegisterManager.all_regs)
- input_i = 0
- for pos in descr.rd_locs:
- if pos == -1:
- continue
- elif pos < GPR_REGS * WORD:
- locs.append(CoreRegisterManager.all_regs[pos // WORD])
- elif pos < (GPR_REGS * WORD + VFP_REGS * DOUBLE_WORD):
- pos = pos // DOUBLE_WORD - GPR_REGS * WORD // DOUBLE_WORD
- locs.append(VFPRegisterManager.all_regs[pos])
- else:
- i = pos // WORD - JITFRAME_FIXED_SIZE
- assert i >= 0
- tp = inputargs[input_i].type
- locs.append(StackLocation(i, pos, tp))
- input_i += 1
- return locs
+ def new_stack_loc(self, i, pos, tp):
+ return StackLocation(i, pos, tp)
def check_frame_before_jump(self, target_token):
if target_token in self.target_tokens_currently_compiling:
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -24,7 +24,7 @@
from rpython.jit.backend.llsupport import symbolic
from rpython.jit.backend.llsupport.gcmap import allocate_gcmap
from rpython.jit.backend.llsupport.descr import InteriorFieldDescr
-from rpython.jit.backend.llsupport.assembler import GuardToken
+from rpython.jit.backend.llsupport.assembler import GuardToken, BaseAssembler
from rpython.jit.metainterp.history import (Box, AbstractFailDescr,
INT, FLOAT, REF)
from rpython.jit.metainterp.history import JitCellToken, TargetToken
@@ -48,7 +48,7 @@
self.offset = offset
-class ResOpAssembler(object):
+class ResOpAssembler(BaseAssembler):
def emit_op_int_add(self, op, arglocs, regalloc, fcond):
return self.int_add_impl(op, arglocs, regalloc, fcond)
diff --git a/rpython/jit/backend/arm/runner.py
b/rpython/jit/backend/arm/runner.py
--- a/rpython/jit/backend/arm/runner.py
+++ b/rpython/jit/backend/arm/runner.py
@@ -1,20 +1,18 @@
from rpython.jit.backend.arm.arch import JITFRAME_FIXED_SIZE
from rpython.jit.backend.arm.assembler import AssemblerARM
-from rpython.jit.backend.arm.registers import all_regs
+from rpython.jit.backend.arm.regalloc import CoreRegisterManager,\
+ VFPRegisterManager
from rpython.jit.backend.llsupport import jitframe
-from rpython.jit.backend.llsupport.symbolic import WORD
from rpython.jit.backend.llsupport.llmodel import AbstractLLCPU
-from rpython.jit.metainterp import history
from rpython.rlib.jit_hooks import LOOP_RUN_CONTAINER
-from rpython.rlib.unroll import unrolling_iterable
-from rpython.rtyper.llinterp import LLInterpreter
-from rpython.rtyper.lltypesystem import lltype, rffi, llmemory
-
+from rpython.rtyper.lltypesystem import lltype, llmemory
jitframe.STATICSIZE = JITFRAME_FIXED_SIZE
class AbstractARMCPU(AbstractLLCPU):
+ IS_64_BIT = False
+
supports_floats = True
supports_longlong = False # XXX requires an implementation of
# read_timestamp that works in user mode
@@ -22,6 +20,8 @@
from rpython.jit.backend.arm.arch import JITFRAME_FIXED_SIZE
all_reg_indexes = range(16)
+ gen_regs = CoreRegisterManager.all_regs
+ float_regs = VFPRegisterManager.all_regs
use_hf_abi = False # use hard float abi flag
diff --git a/rpython/jit/backend/llsupport/assembler.py
b/rpython/jit/backend/llsupport/assembler.py
--- a/rpython/jit/backend/llsupport/assembler.py
+++ b/rpython/jit/backend/llsupport/assembler.py
@@ -36,6 +36,31 @@
gcmap[val // WORD // 8] |= r_uint(1) << (val % (WORD * 8))
return gcmap
+
class BaseAssembler(object):
""" Base class for Assembler generator in real backends
"""
+ def rebuild_faillocs_from_descr(self, descr, inputargs):
+ locs = []
+ GPR_REGS = len(self.cpu.gen_regs)
+ XMM_REGS = len(self.cpu.float_regs)
+ input_i = 0
+ if self.cpu.IS_64_BIT:
+ coeff = 1
+ else:
+ coeff = 2
+ for pos in descr.rd_locs:
+ if pos == -1:
+ continue
+ elif pos < GPR_REGS * WORD:
+ locs.append(self.cpu.gen_regs[pos // WORD])
+ elif pos < (GPR_REGS + XMM_REGS * coeff) * WORD:
+ pos = (pos // WORD - GPR_REGS) // coeff
+ locs.append(self.cpu.float_regs[pos])
+ else:
+ i = pos // WORD - self.cpu.JITFRAME_FIXED_SIZE
+ assert i >= 0
+ tp = inputargs[input_i].type
+ locs.append(self.new_stack_loc(i, pos, tp))
+ input_i += 1
+ return locs
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1926,31 +1926,9 @@
ofs = self.cpu.get_ofs_of_frame_field('jf_gcmap')
mc.MOV_bi(ofs, 0)
- def rebuild_faillocs_from_descr(self, descr, inputargs):
- locs = []
- GPR_REGS = len(gpr_reg_mgr_cls.all_regs)
- XMM_REGS = len(xmm_reg_mgr_cls.all_regs)
+ def new_stack_loc(self, i, pos, tp):
base_ofs = self.cpu.get_baseofs_of_frame_field()
- input_i = 0
- if IS_X86_64:
- coeff = 1
- else:
- coeff = 2
- for pos in descr.rd_locs:
- if pos == -1:
- continue
- elif pos < GPR_REGS * WORD:
- locs.append(gpr_reg_mgr_cls.all_regs[pos // WORD])
- elif pos < (GPR_REGS + XMM_REGS * coeff) * WORD:
- pos = (pos // WORD - GPR_REGS) // coeff
- locs.append(xmm_reg_mgr_cls.all_regs[pos])
- else:
- i = pos // WORD - JITFRAME_FIXED_SIZE
- assert i >= 0
- tp = inputargs[input_i].type
- locs.append(StackLoc(i, get_ebp_ofs(base_ofs, i), tp))
- input_i += 1
- return locs
+ return StackLoc(i, get_ebp_ofs(base_ofs, i), tp)
def setup_failure_recovery(self):
self.failure_recovery_code = [0, 0, 0, 0]
diff --git a/rpython/jit/backend/x86/runner.py
b/rpython/jit/backend/x86/runner.py
--- a/rpython/jit/backend/x86/runner.py
+++ b/rpython/jit/backend/x86/runner.py
@@ -2,7 +2,7 @@
from rpython.rtyper.lltypesystem import lltype, llmemory, rffi
from rpython.rlib.jit_hooks import LOOP_RUN_CONTAINER
from rpython.jit.backend.x86.assembler import Assembler386
-from rpython.jit.backend.x86.regalloc import gpr_reg_mgr_cls
+from rpython.jit.backend.x86.regalloc import gpr_reg_mgr_cls, xmm_reg_mgr_cls
from rpython.jit.backend.x86.profagent import ProfileAgent
from rpython.jit.backend.llsupport.llmodel import AbstractLLCPU
from rpython.jit.backend.x86 import regloc
@@ -24,6 +24,8 @@
from rpython.jit.backend.x86.arch import JITFRAME_FIXED_SIZE
all_reg_indexes = gpr_reg_mgr_cls.all_reg_indexes
+ gen_regs = gpr_reg_mgr_cls.all_regs
+ float_regs = xmm_reg_mgr_cls.all_regs
def __init__(self, rtyper, stats, opts=None, translate_support_code=False,
gcdescr=None):
@@ -128,12 +130,13 @@
class CPU386(AbstractX86CPU):
backend_name = 'x86'
- WORD = 4
NUM_REGS = 8
CALLEE_SAVE_REGISTERS = [regloc.ebx, regloc.esi, regloc.edi]
supports_longlong = True
+ IS_64_BIT = False
+
def __init__(self, *args, **kwargs):
assert sys.maxint == (2**31 - 1)
super(CPU386, self).__init__(*args, **kwargs)
@@ -144,8 +147,9 @@
class CPU_X86_64(AbstractX86CPU):
backend_name = 'x86_64'
- WORD = 8
NUM_REGS = 16
CALLEE_SAVE_REGISTERS = [regloc.ebx, regloc.r12, regloc.r13, regloc.r14,
regloc.r15]
+ IS_64_BIT = True
+
CPU = CPU386
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