Author: David Schneider <david.schnei...@picle.org>
Branch: jitframe-on-heap
Changeset: r61537:3e38be380144
Date: 2013-02-21 14:26 +0100
http://bitbucket.org/pypy/pypy/changeset/3e38be380144/
Log: set ofs by default to 0 in store_reg and load_reg
diff --git a/rpython/jit/backend/arm/assembler.py
b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -993,7 +993,7 @@
self.mc.gen_load_int(r.ip.value, value.getint())
self.mc.VLDR(loc.value, r.ip.value)
- def load_reg(self, mc, target, base, ofs, cond=c.AL, helper=r.ip):
+ def load_reg(self, mc, target, base, ofs=0, cond=c.AL, helper=r.ip):
if target.is_vfp_reg():
return self._load_vfp_reg(mc, target, base, ofs, cond, helper)
elif target.is_reg():
@@ -1014,7 +1014,7 @@
mc.gen_load_int(helper.value, ofs, cond=cond)
mc.LDR_rr(target.value, base.value, helper.value, cond=cond)
- def store_reg(self, mc, source, base, ofs, cond=c.AL, helper=r.ip):
+ def store_reg(self, mc, source, base, ofs=0, cond=c.AL, helper=r.ip):
if source.is_vfp_reg():
return self._store_vfp_reg(mc, source, base, ofs, cond, helper)
else:
_______________________________________________
pypy-commit mailing list
pypy-commit@python.org
http://mail.python.org/mailman/listinfo/pypy-commit
