Author: David Schneider <[email protected]>
Branch:
Changeset: r62857:24fd80198c9d
Date: 2013-03-28 21:30 +0100
http://bitbucket.org/pypy/pypy/changeset/24fd80198c9d/
Log: kill hack and use cpu autodetection to build instruction builder
classes for the corresponding architecture
diff --git a/rpython/jit/backend/arm/assembler.py
b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -5,7 +5,7 @@
from rpython.jit.backend.arm import conditions as c, registers as r
from rpython.jit.backend.arm.arch import (WORD, DOUBLE_WORD, FUNC_ALIGN,
JITFRAME_FIXED_SIZE)
-from rpython.jit.backend.arm.codebuilder import ARMv7Builder,
OverwritingBuilder
+from rpython.jit.backend.arm.codebuilder import InstrBuilder,
OverwritingBuilder
from rpython.jit.backend.arm.locations import imm, StackLocation
from rpython.jit.backend.arm.opassembler import ResOpAssembler
from rpython.jit.backend.arm.regalloc import (Regalloc,
@@ -59,14 +59,13 @@
if we_are_translated():
self.debug = False
self.current_clt = looptoken.compiled_loop_token
- self.mc = ARMv7Builder()
+ self.mc = InstrBuilder()
self.pending_guards = []
assert self.datablockwrapper is None
allblocks = self.get_asmmemmgr_blocks(looptoken)
self.datablockwrapper = MachineDataBlockWrapper(self.cpu.asmmemmgr,
allblocks)
self.mc.datablockwrapper = self.datablockwrapper
- self.mc.is_armv6 = self.cpu.backend_name.startswith('armv6')
self.target_tokens_currently_compiling = {}
def teardown(self):
@@ -157,7 +156,7 @@
if not self.cpu.propagate_exception_descr:
return # not supported (for tests, or non-translated)
#
- mc = ARMv7Builder()
+ mc = InstrBuilder()
self._store_and_reset_exception(mc, r.r0)
ofs = self.cpu.get_ofs_of_frame_field('jf_guard_exc')
# make sure ofs fits into a register
@@ -242,7 +241,7 @@
# | my own retaddr | <-- sp
# +-----------------------+
#
- mc = ARMv7Builder()
+ mc = InstrBuilder()
# save argument registers and return address
mc.PUSH([reg.value for reg in r.argument_regs] + [r.ip.value,
r.lr.value])
# stack is aligned here
@@ -283,7 +282,7 @@
# write barriers. It must save all registers, and optionally
# all vfp registers. It takes a single argument which is in r0.
# It must keep stack alignment accordingly.
- mc = ARMv7Builder()
+ mc = InstrBuilder()
#
exc0 = exc1 = None
mc.PUSH([r.ip.value, r.lr.value]) # push two words to keep alignment
@@ -327,7 +326,7 @@
self.wb_slowpath[withcards + 2 * withfloats] = rawstart
def _build_malloc_slowpath(self):
- mc = ARMv7Builder()
+ mc = InstrBuilder()
self._push_all_regs_to_jitframe(mc, [r.r0, r.r1],
self.cpu.supports_floats)
ofs = self.cpu.get_ofs_of_frame_field('jf_gcmap')
# store the gc pattern
@@ -439,7 +438,7 @@
self.load_reg(mc, vfpr, r.fp, ofs)
def _build_failure_recovery(self, exc, withfloats=False):
- mc = ARMv7Builder()
+ mc = InstrBuilder()
self._push_all_regs_to_jitframe(mc, [], withfloats)
if exc:
@@ -766,7 +765,7 @@
# f) store the address of the new jitframe in the shadowstack
# c) set the gcmap field to 0 in the new jitframe
# g) restore registers and return
- mc = ARMv7Builder()
+ mc = InstrBuilder()
self._push_all_regs_to_jitframe(mc, [], self.cpu.supports_floats)
# this is the gcmap stored by push_gcmap(mov=True) in
_check_stack_frame
# and the expected_size pushed in _check_stack_frame
@@ -826,7 +825,7 @@
self.target_tokens_currently_compiling = None
def _patch_stackadjust(self, adr, allocated_depth):
- mc = ARMv7Builder()
+ mc = InstrBuilder()
mc.gen_load_int(r.lr.value, allocated_depth)
mc.copy_to_raw_memory(adr)
@@ -862,7 +861,7 @@
# patch the guard jumpt to the stub
# overwrite the generate NOP with a B_offs to the pos of the
# stub
- mc = ARMv7Builder()
+ mc = InstrBuilder()
mc.B_offs(relative_offset, c.get_opposite_of(tok.fcond))
mc.copy_to_raw_memory(guard_pos)
else:
@@ -941,7 +940,7 @@
self.mc.ASR_ri(resloc.value, resloc.value, 16)
def patch_trace(self, faildescr, looptoken, bridge_addr, regalloc):
- b = ARMv7Builder()
+ b = InstrBuilder()
patch_addr = faildescr._arm_failure_recovery_block
assert patch_addr != 0
b.B(bridge_addr)
diff --git a/rpython/jit/backend/arm/codebuilder.py
b/rpython/jit/backend/arm/codebuilder.py
--- a/rpython/jit/backend/arm/codebuilder.py
+++ b/rpython/jit/backend/arm/codebuilder.py
@@ -7,6 +7,7 @@
from rpython.rlib.objectmodel import we_are_translated
from rpython.rtyper.lltypesystem import lltype, rffi, llmemory
from rpython.tool.udir import udir
+from rpython.jit.backend.detect_cpu import autodetect
clear_cache = rffi.llexternal(
"__clear_cache",
@@ -30,7 +31,7 @@
class AbstractARMv7Builder(object):
def __init__(self):
- self.is_armv6 = False
+ pass
def align(self):
while(self.currpos() % FUNC_ALIGN != 0):
@@ -245,25 +246,31 @@
def currpos(self):
raise NotImplementedError
+ max_size_of_gen_load_int = 2 * WORD
def gen_load_int(self, r, value, cond=cond.AL):
"""r is the register number, value is the value to be loaded to the
register"""
- if self.is_armv6:
- from pypy.jit.backend.arm.conditions import AL
- if cond != AL or 0 <= value <= 0xFFFF:
- self._load_by_shifting(r, value, cond)
- else:
- self.LDR_ri(r, reg.pc.value)
- self.MOV_rr(reg.pc.value, reg.pc.value)
- self.write32(value)
- else:
- bottom = value & 0xFFFF
- top = value >> 16
- self.MOVW_ri(r, bottom, cond)
- if top:
- self.MOVT_ri(r, top, cond)
+ bottom = value & 0xFFFF
+ top = value >> 16
+ self.MOVW_ri(r, bottom, cond)
+ if top:
+ self.MOVT_ri(r, top, cond)
- max_size_of_gen_load_int = 2 * WORD
+
+class AbstractARMv6Builder(AbstractARMv7Builder):
+
+ def __init__(self):
+ AbstractARMv7Builder.__init__(self)
+
+ def gen_load_int(self, r, value, cond=cond.AL):
+ from pypy.jit.backend.arm.conditions import AL
+ if cond != AL or 0 <= value <= 0xFFFF:
+ self._load_by_shifting(r, value, cond)
+ else:
+ self.LDR_ri(r, reg.pc.value)
+ self.MOV_rr(reg.pc.value, reg.pc.value)
+ self.write32(value)
+
ofs_shift = zip(range(8, 25, 8), range(12, 0, -4))
def _load_by_shifting(self, r, value, c=cond.AL):
# to be sure it is only called for the correct cases
@@ -276,10 +283,15 @@
t = b | (shift << 8)
self.ORR_ri(r, r, imm=t, cond=c)
+if autodetect().startswith('armv7'):
+ AbstractBuilder = AbstractARMv7Builder
+else:
+ AbstractBuilder = AbstractARMv6Builder
-class OverwritingBuilder(AbstractARMv7Builder):
+
+class OverwritingBuilder(AbstractBuilder):
def __init__(self, cb, start, size):
- AbstractARMv7Builder.__init__(self)
+ AbstractBuilder.__init__(self)
self.cb = cb
self.index = start
self.end = start + size
@@ -293,9 +305,9 @@
self.index += 1
-class ARMv7Builder(BlockBuilderMixin, AbstractARMv7Builder):
+class InstrBuilder(BlockBuilderMixin, AbstractBuilder):
def __init__(self):
- AbstractARMv7Builder.__init__(self)
+ AbstractBuilder.__init__(self)
self.init_block_builder()
#
# ResOperation --> offset in the assembly.
@@ -349,4 +361,4 @@
return self.get_relative_pos()
-define_instructions(AbstractARMv7Builder)
+define_instructions(AbstractBuilder)
diff --git a/rpython/jit/backend/arm/helper/assembler.py
b/rpython/jit/backend/arm/helper/assembler.py
--- a/rpython/jit/backend/arm/helper/assembler.py
+++ b/rpython/jit/backend/arm/helper/assembler.py
@@ -1,7 +1,7 @@
from __future__ import with_statement
from rpython.jit.backend.arm import conditions as c
from rpython.jit.backend.arm import registers as r
-from rpython.jit.backend.arm.codebuilder import AbstractARMv7Builder
+from rpython.jit.backend.arm.codebuilder import InstrBuilder
from rpython.jit.metainterp.history import ConstInt, BoxInt, FLOAT
from rpython.rlib.rarithmetic import r_uint, r_longlong, intmask
from rpython.jit.metainterp.resoperation import rop
@@ -34,8 +34,8 @@
return f
def gen_emit_op_ri(name, opname):
- ri_op = getattr(AbstractARMv7Builder, '%s_ri' % opname)
- rr_op = getattr(AbstractARMv7Builder, '%s_rr' % opname)
+ ri_op = getattr(InstrBuilder, '%s_ri' % opname)
+ rr_op = getattr(InstrBuilder, '%s_rr' % opname)
def f(self, op, arglocs, regalloc, fcond):
assert fcond is not None
l0, l1, res = arglocs
@@ -48,7 +48,7 @@
return f
def gen_emit_op_by_helper_call(name, opname):
- helper = getattr(AbstractARMv7Builder, opname)
+ helper = getattr(InstrBuilder, opname)
def f(self, op, arglocs, regalloc, fcond):
assert fcond is not None
if op.result:
@@ -97,7 +97,7 @@
return f
def gen_emit_float_op(name, opname):
- op_rr = getattr(AbstractARMv7Builder, opname)
+ op_rr = getattr(InstrBuilder, opname)
def f(self, op, arglocs, regalloc, fcond):
arg1, arg2, result = arglocs
op_rr(self.mc, result.value, arg1.value, arg2.value)
@@ -105,7 +105,7 @@
f.__name__ = 'emit_op_%s' % name
return f
def gen_emit_unary_float_op(name, opname):
- op_rr = getattr(AbstractARMv7Builder, opname)
+ op_rr = getattr(InstrBuilder, opname)
def f(self, op, arglocs, regalloc, fcond):
arg1, result = arglocs
op_rr(self.mc, result.value, arg1.value)
diff --git a/rpython/jit/backend/arm/helper/regalloc.py
b/rpython/jit/backend/arm/helper/regalloc.py
--- a/rpython/jit/backend/arm/helper/regalloc.py
+++ b/rpython/jit/backend/arm/helper/regalloc.py
@@ -1,6 +1,5 @@
from rpython.jit.backend.arm import conditions as c
from rpython.jit.backend.arm import registers as r
-from rpython.jit.backend.arm.codebuilder import AbstractARMv7Builder
from rpython.jit.metainterp.history import ConstInt, BoxInt, Box, FLOAT
from rpython.jit.metainterp.history import ConstInt
from rpython.rlib.objectmodel import we_are_translated
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -17,7 +17,7 @@
saved_registers,
count_reg_args)
from rpython.jit.backend.arm.helper.regalloc import check_imm_arg
-from rpython.jit.backend.arm.codebuilder import ARMv7Builder,
OverwritingBuilder
+from rpython.jit.backend.arm.codebuilder import InstrBuilder,
OverwritingBuilder
from rpython.jit.backend.arm.jump import remap_frame_layout
from rpython.jit.backend.arm.regalloc import TempInt, TempPtr
from rpython.jit.backend.arm.locations import imm
@@ -1219,7 +1219,7 @@
baseofs = self.cpu.get_baseofs_of_frame_field()
newlooptoken.compiled_loop_token.update_frame_info(
oldlooptoken.compiled_loop_token, baseofs)
- mc = ARMv7Builder()
+ mc = InstrBuilder()
mc.B(target)
mc.copy_to_raw_memory(oldadr)
diff --git a/rpython/jit/backend/arm/runner.py
b/rpython/jit/backend/arm/runner.py
--- a/rpython/jit/backend/arm/runner.py
+++ b/rpython/jit/backend/arm/runner.py
@@ -86,10 +86,10 @@
possible then to re-call invalidate_loop() on the same looptoken,
which must invalidate all newer GUARD_NOT_INVALIDATED, but not the
old one that already has a bridge attached to it."""
- from rpython.jit.backend.arm.codebuilder import ARMv7Builder
+ from rpython.jit.backend.arm.codebuilder import InstrBuilder
for jmp, tgt in looptoken.compiled_loop_token.invalidate_positions:
- mc = ARMv7Builder()
+ mc = InstrBuilder()
mc.B_offs(tgt)
mc.copy_to_raw_memory(jmp)
# positions invalidated
diff --git a/rpython/jit/backend/arm/test/test_calling_convention.py
b/rpython/jit/backend/arm/test/test_calling_convention.py
--- a/rpython/jit/backend/arm/test/test_calling_convention.py
+++ b/rpython/jit/backend/arm/test/test_calling_convention.py
@@ -4,7 +4,7 @@
from rpython.rtyper.lltypesystem import lltype
from rpython.jit.codewriter.effectinfo import EffectInfo
-from rpython.jit.backend.arm.codebuilder import ARMv7Builder
+from rpython.jit.backend.arm.codebuilder import InstrBuilder
from rpython.jit.backend.arm import registers as r
from rpython.jit.backend.arm.test.support import skip_unless_run_slow_tests
from rpython.jit.backend.arm.test.test_runner import boxfloat, constfloat
@@ -25,9 +25,9 @@
# ../../test/calling_convention_test.py
def make_function_returning_stack_pointer(self):
- mc = ARMv7Builder()
- mc.MOV_rr(r.r0.value, r.sp.value)
- mc.MOV_rr(r.pc.value, r.lr.value)
+ mc = InstrBuilder()
+ mc.MOV_rr(r.r0.value, r.sp.value)
+ mc.MOV_rr(r.pc.value, r.lr.value)
return mc.materialize(self.cpu.asmmemmgr, [])
def get_alignment_requirements(self):
diff --git a/rpython/jit/backend/arm/test/test_instr_codebuilder.py
b/rpython/jit/backend/arm/test/test_instr_codebuilder.py
--- a/rpython/jit/backend/arm/test/test_instr_codebuilder.py
+++ b/rpython/jit/backend/arm/test/test_instr_codebuilder.py
@@ -8,7 +8,7 @@
requires_arm_as()
-class CodeBuilder(codebuilder.ARMv7Builder):
+class CodeBuilder(codebuilder.InstrBuilder):
def __init__(self):
self.buffer = []
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