Author: David Schneider <david.schnei...@picle.org>
Branch: armhf-singlefloat
Changeset: r67992:d8b1b0c57e72
Date: 2013-11-12 14:41 -0600
http://bitbucket.org/pypy/pypy/changeset/d8b1b0c57e72/
Log: use single precision operations for casts to and from float
diff --git a/rpython/jit/backend/arm/codebuilder.py
b/rpython/jit/backend/arm/codebuilder.py
--- a/rpython/jit/backend/arm/codebuilder.py
+++ b/rpython/jit/backend/arm/codebuilder.py
@@ -222,8 +222,16 @@
self._VCVT(target, source, cond, 0, 1)
def _VCVT(self, target, source, cond, opc2, sz):
- D = 0
- M = 0
+ # A8.6.295
+ to_integer = (opc2 >> 2) & 1
+ if to_integer:
+ D = target & 1
+ target >>= 1
+ M = (source >> 4) & 1
+ else:
+ M = source & 1
+ source >>= 1
+ D = (target >> 4) & 1
op = 1
instr = (cond << 28
| 0xEB8 << 16
@@ -240,8 +248,8 @@
def _VCVT_single_double(self, target, source, cond, sz):
# double_to_single = (sz == '1');
- D = 0
- M = 0
+ D = target & 1 if sz else (target >> 4) & 1
+ M = (source >> 4) & 1 if sz else source & 1
instr = (cond << 28
| 0xEB7 << 16
| 0xAC << 4
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -1102,17 +1102,16 @@
arg, res = arglocs
assert arg.is_vfp_reg()
assert res.is_core_reg()
- self.mc.VCVT_float_to_int(r.vfp_ip.value, arg.value)
- self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value)
+ self.mc.VCVT_float_to_int(r.svfp_ip.value, arg.value)
+ self.mc.VMOV_sc(res.value, r.svfp_ip.value)
return fcond
def emit_op_cast_int_to_float(self, op, arglocs, regalloc, fcond):
arg, res = arglocs
assert res.is_vfp_reg()
assert arg.is_core_reg()
- self.mc.MOV_ri(r.ip.value, 0)
- self.mc.VMOV_cr(res.value, arg.value, r.ip.value)
- self.mc.VCVT_int_to_float(res.value, res.value)
+ self.mc.VMOV_cs(r.svfp_ip.value, arg.value)
+ self.mc.VCVT_int_to_float(res.value, r.svfp_ip.value)
return fcond
emit_op_llong_add = gen_emit_float_op('llong_add', 'VADD_i64')
@@ -1147,15 +1146,14 @@
arg, res = arglocs
assert arg.is_vfp_reg()
assert res.is_core_reg()
- self.mc.VCVT_f64_f32(r.vfp_ip.value, arg.value)
- self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value)
+ self.mc.VCVT_f64_f32(r.svfp_ip.value, arg.value)
+ self.mc.VMOV_sc(res.value, r.svfp_ip.value)
return fcond
def emit_op_cast_singlefloat_to_float(self, op, arglocs, regalloc, fcond):
arg, res = arglocs
assert res.is_vfp_reg()
assert arg.is_core_reg()
- self.mc.MOV_ri(r.ip.value, 0)
- self.mc.VMOV_cr(res.value, arg.value, r.ip.value)
- self.mc.VCVT_f32_f64(res.value, res.value)
+ self.mc.VMOV_cs(r.svfp_ip.value, arg.value)
+ self.mc.VCVT_f32_f64(res.value, r.svfp_ip.value)
return fcond
diff --git a/rpython/jit/backend/arm/registers.py
b/rpython/jit/backend/arm/registers.py
--- a/rpython/jit/backend/arm/registers.py
+++ b/rpython/jit/backend/arm/registers.py
@@ -23,6 +23,7 @@
lr = r14
pc = r15
vfp_ip = d15
+svfp_ip = s31
all_regs = [r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10]
all_vfp_regs = vfpregisters[:-1]
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