Author: Armin Rigo <[email protected]>
Branch: stmgc-c7
Changeset: r70417:a79b417389c0
Date: 2014-04-03 12:32 +0200
http://bitbucket.org/pypy/pypy/changeset/a79b417389c0/
Log: Fix copystrcontent on stm
diff --git a/rpython/jit/backend/llsupport/stmrewrite.py
b/rpython/jit/backend/llsupport/stmrewrite.py
--- a/rpython/jit/backend/llsupport/stmrewrite.py
+++ b/rpython/jit/backend/llsupport/stmrewrite.py
@@ -125,16 +125,6 @@
return val not in self.write_barrier_applied
- def handle_copystrcontent(self, op):
- xxxxxxxx
- # first, a write barrier on the target string
- lst = op.getarglist()
- lst[1] = self.gen_barrier(lst[1], 'W')
- op = op.copy_and_change(op.getopnum(), args=lst)
- # then an immutable read barrier the source string
- # XXX: 'I' enough?
- self.handle_category_operations(op, 'R')
-
@specialize.arg(1)
def _do_stm_call(self, funcname, args, result):
addr = self.gc_ll_descr.get_malloc_fn_addr(funcname)
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1010,6 +1010,17 @@
self.mc.LEA(result, addr_add(self.SEGMENT_NO, frm, sizereg,
baseofs, scale))
+ def convert_addresses_to_linear(self, reg1, reg2):
+ if not self.cpu.gc_ll_descr.stm: # stm-only
+ return
+ if not IS_X86_64:
+ todo() # "needed for X86_64_SCRATCH_REG"
+ sb_adr = rstm.adr_segment_base
+ assert rx86.fits_in_32bits(sb_adr) # because it is in the 2nd page
+ self.mc.MOV_rj(X86_64_SCRATCH_REG.value, (self.SEGMENT_GC, sb_adr))
+ self.mc.ADD(reg1, X86_64_SCRATCH_REG)
+ self.mc.ADD(reg2, X86_64_SCRATCH_REG)
+
def _unaryop(asmop):
def genop_unary(self, op, arglocs, resloc):
getattr(self.mc, asmop)(arglocs[0])
diff --git a/rpython/jit/backend/x86/regalloc.py
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -1133,6 +1133,8 @@
dstaddr_loc = self.rm.force_allocate_reg(dstaddr_box, forbidden_vars)
self._gen_address_inside_string(base_loc, ofs_loc, dstaddr_loc,
is_unicode=is_unicode)
+ # for stm: convert the addresses from %gs-based to linear
+ self.assembler.convert_addresses_to_linear(srcaddr_loc, dstaddr_loc)
# compute the length in bytes
length_box = args[4]
length_loc = self.loc(length_box)
diff --git a/rpython/rlib/rstm.py b/rpython/rlib/rstm.py
--- a/rpython/rlib/rstm.py
+++ b/rpython/rlib/rstm.py
@@ -20,6 +20,8 @@
CFlexSymbolic('((long)&STM_SEGMENT->transaction_read_version)'))
adr_jmpbuf_ptr = (
CFlexSymbolic('((long)&STM_SEGMENT->jmpbuf_ptr)'))
+adr_segment_base = (
+ CFlexSymbolic('((long)&STM_SEGMENT->segment_base)'))
adr_write_slowpath = CFlexSymbolic('((long)&_stm_write_slowpath)')
adr__pypy_stm_become_inevitable = (
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