[pypy-commit] pypy fast-gil: Re-add MOVD32_xs, MOVD32_sx

[arigo]

Author: Armin Rigo <ar...@tunes.org>
Branch: fast-gil
Changeset: r72193:3bd28cc2fcbb
Date: 2014-06-24 14:51 +0200
http://bitbucket.org/pypy/pypy/changeset/3bd28cc2fcbb/

Log:    Re-add MOVD32_xs, MOVD32_sx

diff --git a/rpython/jit/backend/x86/callbuilder.py 
b/rpython/jit/backend/x86/callbuilder.py
--- a/rpython/jit/backend/x86/callbuilder.py
+++ b/rpython/jit/backend/x86/callbuilder.py
@@ -456,7 +456,7 @@
             return
         #
         if self.restype == 'S':
-            self.mc.MOVD_xs(xmm0.value, 0)
+            self.mc.MOVD32_xs(xmm0.value, 0)
         else:
             assert self.restype == INT
             self.mc.MOV_rs(eax.value, 0)
diff --git a/rpython/jit/backend/x86/rx86.py b/rpython/jit/backend/x86/rx86.py
--- a/rpython/jit/backend/x86/rx86.py
+++ b/rpython/jit/backend/x86/rx86.py
@@ -628,8 +628,10 @@
     MOVDQ_xb = xmminsn('\x66', rex_w, '\x0F\x6E', register(1, 8), stack_bp(2))
 
     MOVD32_rx = xmminsn('\x66', rex_nw, '\x0F\x7E', register(2, 8), 
register(1), '\xC0')
+    MOVD32_sx = xmminsn('\x66', rex_nw, '\x0F\x7E', register(2, 8), 
stack_sp(1))
     MOVD32_xr = xmminsn('\x66', rex_nw, '\x0F\x6E', register(1, 8), 
register(2), '\xC0')
     MOVD32_xb = xmminsn('\x66', rex_nw, '\x0F\x6E', register(1, 8), 
stack_bp(2))
+    MOVD32_xs = xmminsn('\x66', rex_nw, '\x0F\x6E', register(1, 8), 
stack_sp(2))
 
     PSRAD_xi = xmminsn('\x66', rex_nw, '\x0F\x72', register(1), '\xE0', 
immediate(2, 'b'))
 
_______________________________________________
pypy-commit mailing list
pypy-commit@python.org
https://mail.python.org/mailman/listinfo/pypy-commit