Author: Maciej Fijalkowski <[email protected]>
Branch: gc_no_cleanup_nursery
Changeset: r73686:c50bae221df1
Date: 2014-09-25 09:54 +0200
http://bitbucket.org/pypy/pypy/changeset/c50bae221df1/
Log: merge
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -25,7 +25,7 @@
from rpython.jit.backend.llsupport.descr import InteriorFieldDescr
from rpython.jit.backend.llsupport.assembler import GuardToken, BaseAssembler
from rpython.jit.backend.llsupport.regalloc import get_scale
-from rpython.jit.metainterp.history import (Box, AbstractFailDescr,
+from rpython.jit.metainterp.history import (Box, AbstractFailDescr, ConstInt,
INT, FLOAT, REF)
from rpython.jit.metainterp.history import TargetToken
from rpython.jit.metainterp.resoperation import rop
@@ -1175,3 +1175,84 @@
self.mc.VMOV_cs(r.svfp_ip.value, arg.value)
self.mc.VCVT_f32_f64(res.value, r.svfp_ip.value)
return fcond
+
+ #from ../x86/regalloc.py:1388
+ def emit_op_zero_array(self, op, arglocs, regalloc, fcond):
+ from rpython.jit.backend.llsupport.descr import unpack_arraydescr
+ assert len(arglocs) == 0
+ itemsize, baseofs, _ = unpack_arraydescr(op.getdescr())
+ args = op.getarglist()
+ base_loc = regalloc.rm.make_sure_var_in_reg(args[0], args)
+ sibox = args[1]
+ if isinstance(sibox, ConstInt):
+ startindex_loc = None
+ startindex = sibox.getint()
+ assert startindex >= 0
+ else:
+ startindex_loc = regalloc.rm.make_sure_var_in_reg(sibox, args)
+ startindex = -1
+ length_box = op.getarg(2)
+
+ # base_loc and startindex_loc are in two regs here (or they are
+ # immediates). Compute the dstaddr_loc, which is the raw
+ # address that we will pass as first argument to memset().
+ # It can be in the same register as either one, but not in
+ # args[2], because we're still needing the latter.
+ dstaddr_box = TempBox()
+ dstaddr_loc = regalloc.rm.force_allocate_reg(dstaddr_box, [args[2]])
+ if startindex >= 0: # a constant
+ ofs = baseofs + startindex * itemsize
+ reg = base_loc.value
+ else:
+ self.mc.gen_load_int(r.ip.value, itemsize)
+ self.mc.MLA(dstaddr_loc.value, r.ip.value,
+ startindex_loc.value, base_loc.value)
+ ofs = baseofs
+ reg = dstaddr_loc.value
+ if check_imm_arg(ofs):
+ self.mc.ADD_ri(dstaddr_loc.value, reg, imm=ofs)
+ else:
+ self.mc.gen_load_int(r.ip.value, ofs)
+ self.mc.ADD_rr(dstaddr_loc.value, reg, r.ip.value)
+
+ if (isinstance(length_box, ConstInt) and
+ length_box.getint() <= 14 and # same limit as GCC
+ itemsize in (4, 2, 1)):
+ # Inline a series of STR operations, starting at 'dstaddr_loc'.
+ # XXX we could optimize STRB/STRH into STR, but this needs care:
+ # XXX it only works if startindex_loc is a constant, otherwise
+ # XXX we'd be doing unaligned accesses
+ self.mc.gen_load_int(r.ip.value, 0)
+ for i in range(length_box.getint()):
+ if itemsize == 4:
+ self.mc.STR_ri(r.ip.value, dstaddr_loc.value, imm=i*4)
+ elif itemsize == 2:
+ self.mc.STRH_ri(r.ip.value, dstaddr_loc.value, imm=i*2)
+ else:
+ self.mc.STRB_ri(r.ip.value, dstaddr_loc.value, imm=i*1)
+
+ else:
+ if isinstance(length_box, ConstInt):
+ length_loc = imm(length_box.getint() * itemsize)
+ else:
+ # load length_loc in a register different than dstaddr_loc
+ length_loc = regalloc.rm.make_sure_var_in_reg(length_box,
+ [dstaddr_box])
+ if itemsize > 1:
+ # we need a register that is different from dstaddr_loc,
+ # but which can be identical to length_loc (as usual,
+ # only if the length_box is not used by future operations)
+ bytes_box = TempBox()
+ bytes_loc = regalloc.rm.force_allocate_reg(bytes_box,
+ [dstaddr_box])
+ self.mc.gen_load_int(r.ip.value, itemsize)
+ self.mc.MUL(bytes_loc.value, r.ip.value, length_loc.value)
+ length_box = bytes_box
+ length_loc = bytes_loc
+ #
+ # call memset()
+ regalloc.before_call()
+ self.simple_call_no_collect(imm(self.memset_addr),
+ [dstaddr_loc, imm(0), length_loc])
+ regalloc.rm.possibly_free_var(length_box)
+ regalloc.rm.possibly_free_var(dstaddr_box)
diff --git a/rpython/jit/backend/arm/regalloc.py
b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -996,6 +996,7 @@
prepare_op_copystrcontent = void
prepare_op_copyunicodecontent = void
+ prepare_op_zero_array = void
def prepare_op_unicodelen(self, op, fcond):
l0 = self.make_sure_var_in_reg(op.getarg(0))
diff --git a/rpython/jit/backend/test/runner_test.py
b/rpython/jit/backend/test/runner_test.py
--- a/rpython/jit/backend/test/runner_test.py
+++ b/rpython/jit/backend/test/runner_test.py
@@ -4515,10 +4515,8 @@
for cls2 in [ConstInt, BoxInt]:
print 'a_int:', a_int
print 'of:', OF
- print 'start:', start
- print 'length:', length
- print 'cls1:', cls1.__name__
- print 'cls2:', cls2.__name__
+ print 'start:', cls1.__name__, start
+ print 'length:', cls2.__name__, length
for i in range(100):
if OF == PAIR:
a[i].a = a[i].b = -123456789
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -2376,7 +2376,8 @@
scale = get_scale(itemsize_loc.value)
else:
assert isinstance(startindex_loc, ImmedLoc)
- assert startindex_loc.value == 0
+ baseofs += startindex_loc.value * itemsize_loc.value
+ startindex_loc = imm0
scale = 0
null_reg_cleared = False
i = 0
diff --git a/rpython/jit/backend/x86/regalloc.py
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -1397,8 +1397,7 @@
constbytes = -1
if 0 <= constbytes <= 16 * 8 and (
valid_addressing_size(itemsize) or
- (isinstance(startindex_loc, ImmedLoc) and
- startindex_loc.value == 0)):
+- isinstance(startindex_loc, ImmedLoc)):
if IS_X86_64:
null_loc = X86_64_XMM_SCRATCH_REG
else:
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