Author: Remi Meier <remi.me...@inf.ethz.ch>
Branch: stmgc-c8
Changeset: r76351:4dbf5a92f9f6
Date: 2015-03-12 11:36 +0100
http://bitbucket.org/pypy/pypy/changeset/4dbf5a92f9f6/
Log: fix memset usage in the jit for %gs prefix'd address
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1102,7 +1102,7 @@
self.mc.LEA(result, addr_add(self.SEGMENT_NO, frm, sizereg,
baseofs, scale))
- def convert_addresses_to_linear(self, reg1, reg2):
+ def convert_addresses_to_linear(self, reg1, reg2=None):
if not self.cpu.gc_ll_descr.stm: # stm-only
return
if not IS_X86_64:
@@ -1111,7 +1111,8 @@
assert rx86.fits_in_32bits(sb_adr) # because it is in the 2nd page
self.mc.MOV_rj(X86_64_SCRATCH_REG.value, (self.SEGMENT_GC, sb_adr))
self.mc.ADD(reg1, X86_64_SCRATCH_REG)
- self.mc.ADD(reg2, X86_64_SCRATCH_REG)
+ if reg2 is not None:
+ self.mc.ADD(reg2, X86_64_SCRATCH_REG)
def _unaryop(asmop):
def genop_unary(self, op, arglocs, resloc):
diff --git a/rpython/jit/backend/x86/regalloc.py
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -1461,6 +1461,8 @@
dstaddr_loc, startindex_loc, itemsize_loc,
base_loc, imm(baseofs))
self.assembler.mc.LEA(dstaddr_loc, dst_addr)
+ # for stm: convert the address from %gs-based to linear
+ self.assembler.convert_addresses_to_linear(dstaddr_loc)
#
if constbytes >= 0:
length_loc = imm(constbytes)
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