Author: Armin Rigo <[email protected]>
Branch:
Changeset: r79476:d8ef26e72e17
Date: 2015-09-06 14:16 +0200
http://bitbucket.org/pypy/pypy/changeset/d8ef26e72e17/
Log: oops. I broke the arm backend in 995518da4059 (found by running
test_zll_stress)
diff --git a/rpython/jit/backend/arm/assembler.py
b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -937,7 +937,7 @@
opnum = op.getopnum()
if op.has_no_side_effect() and op.result not in regalloc.longevity:
regalloc.possibly_free_vars_for_op(op)
- if not we_are_translated() and op.getopnum() == -124:
+ elif not we_are_translated() and op.getopnum() == -124:
regalloc.prepare_force_spill(op, fcond)
else:
arglocs = regalloc_operations[opnum](regalloc, op, fcond)
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