Author: Armin Rigo <[email protected]>
Branch:
Changeset: r80138:802959e767cc
Date: 2015-10-12 17:08 +0200
http://bitbucket.org/pypy/pypy/changeset/802959e767cc/
Log: Untested: ARM support
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -508,6 +508,20 @@
self._store_and_reset_exception(self.mc, resloc)
return fcond
+ def emit_op_save_exc_class(self, op, arglocs, regalloc, fcond):
+ resloc = arglocs[0]
+ self.mc.gen_load_int(r.ip.value, self.cpu.pos_exception())
+ self.load_reg(self.mc, resloc, r.ip)
+ return fcond
+
+ def emit_op_save_exception(self, op, arglocs, regalloc, fcond):
+ self._store_and_reset_exception(self.mc, resloc)
+ return fcond
+
+ def emit_op_restore_exception(self, op, arglocs, regalloc, fcond):
+ self._restore_exception(self.mc, arglocs[1], arglocs[0])
+ return fcond
+
def emit_op_debug_merge_point(self, op, arglocs, regalloc, fcond):
return fcond
emit_op_jit_debug = emit_op_debug_merge_point
diff --git a/rpython/jit/backend/arm/regalloc.py
b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -707,6 +707,17 @@
[loc, loc1, resloc, pos_exc_value, pos_exception])
return arglocs
+ def prepare_op_save_exception(self, op, fcond):
+ resloc = self.force_allocate_reg(op)
+ return [resloc]
+ prepare_op_save_exc_class = prepare_op_save_exception
+
+ def prepare_op_restore_exception(self, op, fcond):
+ boxes = op.getarglist()
+ loc0 = self.make_sure_var_in_reg(op.getarg(0), boxes) # exc class
+ loc1 = self.make_sure_var_in_reg(op.getarg(1), boxes) # exc instance
+ return [loc0, loc1]
+
def prepare_op_guard_no_exception(self, op, fcond):
loc = self.make_sure_var_in_reg(ConstInt(self.cpu.pos_exception()))
arglocs = self._prepare_guard(op, [loc])
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