Author: Richard Plangger <planri...@gmail.com>
Branch: s390x-backend
Changeset: r80279:bfd63406a3e9
Date: 2015-10-16 17:18 +0200
http://bitbucket.org/pypy/pypy/changeset/bfd63406a3e9/
Log: rs encoding and rsy (extended version of rs)
diff --git a/rpython/jit/backend/zarch/codebuilder.py
b/rpython/jit/backend/zarch/codebuilder.py
--- a/rpython/jit/backend/zarch/codebuilder.py
+++ b/rpython/jit/backend/zarch/codebuilder.py
@@ -38,10 +38,13 @@
r/m - register or mask
iX - immediate X bits (signed)
uX - immediate X bits (unsigend)
- bd - base displacement
+ bd - base displacement (12 bit)
+ bdl - base displacement long (20 bit)
ibd - index base displacement
l4bd - length base displacement (4 bit)
l8bd - length base displacement (8 bit)
+
+ note that a suffix 'l' means long, and a prefix length
"""
def impl(func):
func._arguments_ = args_str.split(',')
@@ -55,12 +58,32 @@
@always_inline
def encode_base_displace(mc, base_displace):
- displace = base_displace.displace # & 0x3ff
+ """
+ +---------------------------------+
+ | ... | base | length[0:11] | ... |
+ +---------------------------------+
+ """
+ displace = base_displace.displace
base = base_displace.base & 0xf
byte = (displace >> 8 & 0xf) | base << 4
mc.writechar(chr(byte))
mc.writechar(chr(displace & 0xff))
+@always_inline
+def encode_base_displace_long(mc, basedisp):
+ """
+ +-------------------------------------------------+
+ | ... | base | length[0:11] | length[12:20] | ... |
+ +-------------------------------------------------+
+ """
+ displace = basedisp.displace & 0xfffff
+ base = basedisp.base & 0xf
+ byte = displace >> 8 & 0xf | base << 4
+ mc.writechar(chr(byte))
+ mc.writechar(chr(displace & 0xff))
+ byte = displace >> 12 & 0xff
+ mc.writechar(chr(byte))
+
def build_rr(mnemonic, (opcode,)):
@builder.arguments('r,r')
def encode_rr(self, reg1, reg2):
@@ -101,13 +124,7 @@
index = idxbasedisp.index
byte = (reg_or_mask & 0x0f) << 4 | index & 0xf
self.writechar(chr(byte))
- displace = idxbasedisp.displace & 0xfffff
- base = idxbasedisp.base & 0xf
- byte = displace >> 8 & 0xf | base << 4
- self.writechar(chr(byte))
- self.writechar(chr(displace & 0xff))
- byte = displace >> 12 & 0xff
- self.writechar(chr(byte))
+ encode_base_displace_long(self, idxbasedisp)
self.writechar(opcode2)
return encode_rxy
@@ -122,7 +139,7 @@
return encode_ri
def build_ril(mnemonic, (opcode,halfopcode)):
- @builder.arguments('r/m,a32')
+ @builder.arguments('r/m,i32')
def encode_ri(self, reg_or_mask, imm32):
self.writechar(opcode)
byte = (reg_or_mask & 0xf) << 4 | (ord(halfopcode) & 0xf)
@@ -209,6 +226,23 @@
encode_base_displace(self, len_base_disp)
return encode_ssf
+def build_rs(mnemonic, (opcode,)):
+ @builder.arguments('r,r,bd')
+ def encode_rs(self, reg1, reg3, base_displace):
+ self.writechar(opcode)
+ self.writechar(chr((reg1 & BIT_MASK_4) << 4 | reg3 & BIT_MASK_4))
+ encode_base_displace(self, base_displace)
+ return encode_rs
+
+def build_rsy(mnemonic, (opcode1,opcode2)):
+ @builder.arguments('r,r,bdl')
+ def encode_ssa(self, reg1, reg3, base_displace):
+ self.writechar(opcode1)
+ self.writechar(chr((reg1 & BIT_MASK_4) << 4 | reg3 & BIT_MASK_4))
+ encode_base_displace_long(self, base_displace)
+ self.writechar(opcode2)
+ return encode_ssa
+
_mnemonic_codes = {
'AR': (build_rr, ['\x1A']),
'AGR': (build_rre, ['\xB9\x08']),
@@ -227,6 +261,8 @@
'LMD': (build_sse, ['\xEF']),
'PKA': (build_ssf, ['\xE9']),
'BRASL': (build_ril, ['\xC0','\x05']),
+ 'BXH': (build_rs, ['\x86']),
+ 'BXHG': (build_rsy, ['\xEB','\x44']),
}
def build_instr_codes(clazz):
diff --git a/rpython/jit/backend/zarch/test/test_auto_encoding.py
b/rpython/jit/backend/zarch/test/test_auto_encoding.py
--- a/rpython/jit/backend/zarch/test/test_auto_encoding.py
+++ b/rpython/jit/backend/zarch/test/test_auto_encoding.py
@@ -102,7 +102,7 @@
__repr__ = __str__
-def test_range(bits, signed=False, count=24, alignment=0):
+def test_range(bits, signed=False, count=24):
if isinstance(bits, tuple):
bits, signed = bits
if signed:
@@ -132,7 +132,6 @@
'i8': test_range(8, signed=True),
'i16': test_range(16, signed=True),
'i32': test_range(32, signed=True),
- 'a32': test_range(32, signed=True, alignment=16),
'i64': test_range(64, signed=True),
'u4': test_range(4),
'u8': test_range(8),
@@ -140,6 +139,7 @@
'u32': test_range(32),
'u64': test_range(64),
'bd': build_fake(FakeBaseDisplace,4,12),
+ 'bdl': build_fake(FakeBaseDisplace,4,19),
'ibd': build_fake(FakeIndexBaseDisplace,4,4,12),
'ibdl': build_fake(FakeIndexBaseDisplace,4,4,(20,True)),
'l8bd': build_fake(FakeLengthBaseDisplace,8,4,12),
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