Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r80646:ec0e146d57f6
Date: 2015-11-12 13:41 +0100
http://bitbucket.org/pypy/pypy/changeset/ec0e146d57f6/
Log: added regalloc/assembler for shift & logic operations, tested them
in a very basic trace
diff --git a/rpython/jit/backend/zarch/helper/assembler.py
b/rpython/jit/backend/zarch/helper/assembler.py
--- a/rpython/jit/backend/zarch/helper/assembler.py
+++ b/rpython/jit/backend/zarch/helper/assembler.py
@@ -67,3 +67,25 @@
def f(self, op, arglocs, regalloc):
do_emit_cmp_op(self, arglocs, condition, signed, fp)
return f
+
+def gen_emit_shift(func):
+ def f(self, op, arglocs, regalloc):
+ l0, l1 = arglocs
+ if not l1.is_imm() or l1.is_in_pool():
+ assert "shift imm must NOT reside in pool!"
+ getattr(self.mc, func)(l0, l0, l1)
+ return f
+
+def gen_emit_rr_or_rpool(rr_func, rp_func):
+ """ the parameters can either be both in registers or
+ the first is in the register, second in literal pool.
+ """
+ def f(self, op, arglocs, regalloc):
+ l0, l1 = arglocs
+ if l1.is_imm():
+ assert "logical imm must reside in pool!"
+ elif l1.is_in_pool():
+ getattr(self.mc, rp_func)(l0, l1)
+ else:
+ getattr(self.mc, rr_func)(l0, l1)
+ return f
diff --git a/rpython/jit/backend/zarch/helper/regalloc.py
b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -1,5 +1,5 @@
from rpython.jit.metainterp.history import ConstInt, FLOAT
-from rpython.jit.backend.zarch.locations import imm
+from rpython.jit.backend.zarch.locations import imm, addr
def check_imm(arg, lower_bound=-2**15, upper_bound=2**15-1):
if isinstance(arg, ConstInt):
@@ -10,6 +10,9 @@
def check_imm32(arg):
return check_imm(arg, -2**31, 2**31-1)
+def check_imm20(arg):
+ return check_imm(arg, -2**19, 2**19-1)
+
def prepare_int_add(self, op):
a0 = op.getarg(0)
a1 = op.getarg(1)
@@ -56,7 +59,6 @@
self.free_op_vars()
return [lr, lq, l1]
-
def prepare_int_sub(self, op):
a0 = op.getarg(0)
a1 = op.getarg(1)
@@ -68,6 +70,31 @@
self.free_op_vars()
return [l0, l1]
+def prepare_int_logic(self, op):
+ a0 = op.getarg(0)
+ a1 = op.getarg(1)
+ if isinstance(a0, ConstInt):
+ a0, a1 = a1, a0
+ l0 = self.ensure_reg(a0)
+ l1 = self.ensure_reg(a1)
+ self.force_result_in_reg(op, a0)
+ self.free_op_vars()
+ return [l0, l1]
+
+def prepare_int_shift(self, op):
+ a0 = op.getarg(0)
+ a1 = op.getarg(1)
+ assert isinstance(a1, ConstInt)
+ l1 = self.ensure_reg(a1)
+ assert check_imm20(a1)
+ l0 = self.ensure_reg(a0)
+ # note that the shift value is stored
+ # in the addr part of the instruction
+ l1 = addr(a1.getint())
+ self.force_result_in_reg(op, a0)
+ self.free_op_vars()
+ return [l0, l1]
+
def prepare_cmp_op(self, op):
a0 = op.getarg(0)
a1 = op.getarg(1)
diff --git a/rpython/jit/backend/zarch/instructions.py
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -29,8 +29,13 @@
'DSG': ('rxy', ['\xE3','\x0D'], 'eo,bidl'),
'DLGR': ('rre', ['\xB9','\x97'], 'eo,r'),
'DLG': ('rxy', ['\xE3','\x87'], 'eo,bidl'),
+ # there is no immidiate divide
- # there is no immidiate divide
+ # shifting
+ 'SRAG': ('rsy', ['\xEB','\x0A']),
+ 'SLAG': ('rsy', ['\xEB','\x0B']),
+ 'SRLG': ('rsy', ['\xEB','\x0C']),
+ 'SLLG': ('rsy', ['\xEB','\x0D']),
# div
diff --git a/rpython/jit/backend/zarch/opassembler.py
b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -1,4 +1,5 @@
-from rpython.jit.backend.zarch.helper.assembler import gen_emit_cmp_op
+from rpython.jit.backend.zarch.helper.assembler import (gen_emit_cmp_op,
+ gen_emit_rr_or_rpool, gen_emit_shift)
from rpython.jit.backend.zarch.codebuilder import ZARCHGuardToken
import rpython.jit.backend.zarch.conditions as c
import rpython.jit.backend.zarch.registers as r
@@ -72,6 +73,14 @@
else:
self.mc.SGR(l0, l1)
+ emit_int_and = gen_emit_rr_or_rpool("NGR", "NG")
+ emit_int_or = gen_emit_rr_or_rpool("OGR", "OG")
+ emit_int_xor = gen_emit_rr_or_rpool("XGR", "XG")
+
+ emit_int_rshift = gen_emit_shift("SRAG")
+ emit_int_lshift = gen_emit_shift("SLAG")
+ emit_uint_rshift = gen_emit_shift("SRLG")
+
emit_int_le = gen_emit_cmp_op(c.LE)
emit_int_lt = gen_emit_cmp_op(c.LT)
emit_int_gt = gen_emit_cmp_op(c.GT)
diff --git a/rpython/jit/backend/zarch/regalloc.py
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -540,6 +540,14 @@
prepare_uint_floordiv = helper.prepare_int_div
prepare_int_mod = helper.prepare_int_mod
+ prepare_int_and = helper.prepare_int_logic
+ prepare_int_or = helper.prepare_int_logic
+ prepare_int_xor = helper.prepare_int_logic
+
+ prepare_int_rshift = helper.prepare_int_shift
+ prepare_int_lshift = helper.prepare_int_shift
+ prepare_uint_rshift = helper.prepare_int_shift
+
prepare_int_le = helper.prepare_cmp_op
prepare_int_lt = helper.prepare_cmp_op
prepare_int_ge = helper.prepare_cmp_op
diff --git a/rpython/jit/backend/zarch/test/test_runner.py
b/rpython/jit/backend/zarch/test/test_runner.py
--- a/rpython/jit/backend/zarch/test/test_runner.py
+++ b/rpython/jit/backend/zarch/test/test_runner.py
@@ -34,6 +34,14 @@
(1,'i1 = uint_floordiv(i0, 1)', 1),
(30,'i1 = int_mod(i0, 2)', 0),
(1,'i1 = int_mod(i0, 2)', 1),
+ (1,'i1 = int_lshift(i0, 4)', 16),
+ (1,'i1 = int_lshift(i0, 0)', 1),
+ (4,'i1 = int_rshift(i0, 0)', 4),
+ (4,'i1 = int_rshift(i0, 1)', 2),
+ (-1,'i1 = int_rshift(i0, 0)', -1),
+ (-1,'i1 = int_lshift(i0, 1)', -2),
+ (-2**35,'i1 = int_lshift(i0, 1)', (-2**35)*2),
+ (2**64-1,'i1 = uint_rshift(i0, 2)', (2**64-1)//4),
])
def test_int_arithmetic_and_logic(self, value, opcode, result):
loop = parse("""
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