Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r80769:fff20ae97c0f
Date: 2015-11-19 11:28 +0100
http://bitbucket.org/pypy/pypy/changeset/fff20ae97c0f/

Log:    added assembler regalloc/instructions for int_to_float (+ inverse)
        and int_to_ptr (+ inverse). test_runner.py passing 4 more tests

diff --git a/rpython/jit/backend/zarch/assembler.py 
b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -15,7 +15,7 @@
         RECOVERY_TARGET_POOL_OFFSET, JUMPABS_TARGET_ADDR__POOL_OFFSET,
         JUMPABS_POOL_ADDR_POOL_OFFSET)
 from rpython.jit.backend.zarch.opassembler import (IntOpAssembler,
-    FloatOpAssembler, GuardOpAssembler)
+    FloatOpAssembler, GuardOpAssembler, MiscOpAssembler)
 from rpython.jit.backend.zarch.regalloc import Regalloc
 from rpython.jit.metainterp.resoperation import rop
 from rpython.rlib.debug import (debug_print, debug_start, debug_stop,
@@ -31,7 +31,7 @@
 
 class AssemblerZARCH(BaseAssembler,
         IntOpAssembler, FloatOpAssembler,
-        GuardOpAssembler):
+        GuardOpAssembler, MiscOpAssembler):
 
     def __init__(self, cpu, translate_support_code=False):
         BaseAssembler.__init__(self, cpu, translate_support_code)
diff --git a/rpython/jit/backend/zarch/codebuilder.py 
b/rpython/jit/backend/zarch/codebuilder.py
--- a/rpython/jit/backend/zarch/codebuilder.py
+++ b/rpython/jit/backend/zarch/codebuilder.py
@@ -147,12 +147,15 @@
 
 
     def load_imm(self, dest_reg, word):
-        if word <= 32767 and word >= -32768:
+        if -32768 <= word <= 32767:
             self.LGHI(dest_reg, l.imm(word))
-        elif word <= 2**31-1 and word >= -2**31:
+        elif -2**31 <= word <= 2**31-1:
             self.LGFI(dest_reg, l.imm(word))
         else:
-            xxx
+            # this is not put into the constant pool, because it
+            # is an immediate value that cannot easily be estimated
+            self.LGFI(dest_reg, l.imm(word & 0xFFFFffff))
+            self.IIHF(dest_reg, l.imm((word >> 32) & 0xFFFFffff))
 
 _classes = (AbstractZARCHBuilder,)
 
diff --git a/rpython/jit/backend/zarch/conditions.py 
b/rpython/jit/backend/zarch/conditions.py
--- a/rpython/jit/backend/zarch/conditions.py
+++ b/rpython/jit/backend/zarch/conditions.py
@@ -12,6 +12,8 @@
 NO = loc.imm(0xe) # NO overflow
 ANY = loc.imm(0xf)
 
+FP_CUTOFF = loc.imm(0x1) # 4.4 => 4, 4.5 => 4
+
 cond_none = loc.imm(0x0)
 
 @specialize.arg(1)
diff --git a/rpython/jit/backend/zarch/helper/regalloc.py 
b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -165,6 +165,14 @@
     a0 = op.getarg(0)
     assert not isinstance(a0, ConstInt)
     l0 = self.ensure_reg(a0)
-    self.force_result_in_reg(op, a0)
+    res = self.force_result_in_reg(op, a0)
     self.free_op_vars()
-    return [l0]
+    return [l0,]
+
+def prepare_same_as(self, op):
+    a0 = op.getarg(0)
+    assert not isinstance(a0, ConstInt)
+    l0 = self.ensure_reg(a0)
+    res = self.force_allocate_reg(op)
+    self.free_op_vars()
+    return [l0, res]
diff --git a/rpython/jit/backend/zarch/instructions.py 
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -124,6 +124,7 @@
     'LGR':     ('rre',   ['\xB9','\x04']),
     'LG':      ('rxy',   ['\xE3','\x04']),
     'LARL':    ('ril',   ['\xC0','\x00'], 'r/m,h32'),
+    'IIHF':    ('ril',   ['\xC0','\x08']),
 
     # load on condition
     'LOCGR':  ('rrf_c',    ['\xB9','\xE2']),
diff --git a/rpython/jit/backend/zarch/opassembler.py 
b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -201,6 +201,14 @@
         else:
             self.mc.DDBR(l0, l1)
 
+    def emit_cast_float_to_int(self, op, arglocs, regalloc):
+        f0, r0 = arglocs
+        self.mc.CGDBR(r0, f0, c.FP_CUTOFF)
+
+    def emit_cast_int_to_float(self, op, arglocs, regalloc):
+        r0, f0 = arglocs
+        self.mc.CDGBR(f0, r0)
+
 class GuardOpAssembler(object):
     _mixin_ = True
 
@@ -389,3 +397,16 @@
         self._store_force_index(op)
         self.store_info_on_descr(0, guard_token)
 
+class MiscOpAssembler(object):
+    _mixin_ = True
+
+    def _genop_same_as(self, op, arglocs, regalloc):
+        argloc, resloc = arglocs
+        if argloc is not resloc:
+            self.regalloc_mov(argloc, resloc)
+
+    emit_same_as_i = _genop_same_as
+    emit_same_as_r = _genop_same_as
+    emit_same_as_f = _genop_same_as
+    emit_cast_ptr_to_int = _genop_same_as
+    emit_cast_int_to_ptr = _genop_same_as
diff --git a/rpython/jit/backend/zarch/regalloc.py 
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -661,6 +661,20 @@
     prepare_float_mul = helper.prepare_binary_op
     prepare_float_truediv = helper.prepare_binary_op
 
+    prepare_cast_ptr_to_int = helper.prepare_same_as
+    prepare_cast_int_to_ptr = helper.prepare_same_as
+
+    def prepare_cast_int_to_float(self, op):
+        loc1 = self.ensure_reg(op.getarg(0))
+        res = self.fprm.force_allocate_reg(op)
+        return [loc1, res]
+
+    def prepare_cast_float_to_int(self, op):
+        loc1 = self.ensure_reg(op.getarg(0))
+        self.free_op_vars()
+        res = self.rm.force_allocate_reg(op)
+        return [loc1, res]
+
     def _prepare_guard(self, op, args=None):
         if args is None:
             args = []
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