Author: Armin Rigo <[email protected]>
Branch:
Changeset: r81404:bc29b98d120a
Date: 2015-12-20 10:27 +0100
http://bitbucket.org/pypy/pypy/changeset/bc29b98d120a/
Log: untested: adapt the ARM backend to gc_load/gc_store
diff --git a/rpython/jit/backend/arm/opassembler.py
b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -19,7 +19,6 @@
from rpython.jit.backend.arm.locations import imm, RawSPStackLocation
from rpython.jit.backend.llsupport import symbolic
from rpython.jit.backend.llsupport.gcmap import allocate_gcmap
-from rpython.jit.backend.llsupport.descr import InteriorFieldDescr
from rpython.jit.backend.llsupport.assembler import GuardToken, BaseAssembler
from rpython.jit.backend.llsupport.regalloc import get_scale
from rpython.jit.metainterp.history import (AbstractFailDescr, ConstInt,
@@ -655,31 +654,24 @@
pmc.B_offs(offset, c.EQ)
return fcond
- def emit_op_setfield_gc(self, op, arglocs, regalloc, fcond):
- value_loc, base_loc, ofs, size = arglocs
- scale = get_scale(size.value)
- self._write_to_mem(value_loc, base_loc,
- ofs, imm(scale), fcond)
+ def emit_op_gc_store(self, op, arglocs, regalloc, fcond):
+ value_loc, base_loc, ofs_loc, size_loc = arglocs
+ scale = get_scale(size_loc.value)
+ self._write_to_mem(value_loc, base_loc, ofs_loc, imm(scale), fcond)
return fcond
- emit_op_setfield_raw = emit_op_setfield_gc
- emit_op_zero_ptr_field = emit_op_setfield_gc
-
- def _genop_getfield(self, op, arglocs, regalloc, fcond):
- base_loc, ofs, res, size = arglocs
- signed = op.getdescr().is_field_signed()
- scale = get_scale(size.value)
- self._load_from_mem(res, base_loc, ofs, imm(scale), signed, fcond)
+ def _emit_op_gc_load(self, op, arglocs, regalloc, fcond):
+ base_loc, ofs_loc, res_loc, nsize_loc = arglocs
+ nsize = nsize_loc.value
+ signed = (nsize < 0)
+ scale = get_scale(abs(nsize))
+ self._load_from_mem(res_loc, base_loc, ofs_loc, imm(scale),
+ signed, fcond)
return fcond
- emit_op_getfield_gc_i = _genop_getfield
- emit_op_getfield_gc_r = _genop_getfield
- emit_op_getfield_gc_f = _genop_getfield
- emit_op_getfield_gc_pure_i = _genop_getfield
- emit_op_getfield_gc_pure_r = _genop_getfield
- emit_op_getfield_gc_pure_f = _genop_getfield
- emit_op_getfield_raw_i = _genop_getfield
- emit_op_getfield_raw_f = _genop_getfield
+ emit_op_gc_load_i = _emit_op_gc_load
+ emit_op_gc_load_r = _emit_op_gc_load
+ emit_op_gc_load_f = _emit_op_gc_load
def emit_op_increment_debug_counter(self, op, arglocs, regalloc, fcond):
base_loc, value_loc = arglocs
@@ -688,68 +680,21 @@
self.mc.STR_ri(value_loc.value, base_loc.value, 0, cond=fcond)
return fcond
- def _genop_getinteriorfield(self, op, arglocs, regalloc, fcond):
- (base_loc, index_loc, res_loc,
- ofs_loc, ofs, itemsize, fieldsize) = arglocs
- scale = get_scale(fieldsize.value)
- tmploc, save = self.get_tmp_reg([base_loc, ofs_loc])
- assert not save
- self.mc.gen_load_int(tmploc.value, itemsize.value)
- self.mc.MUL(tmploc.value, index_loc.value, tmploc.value)
- descr = op.getdescr()
- assert isinstance(descr, InteriorFieldDescr)
- signed = descr.fielddescr.is_field_signed()
- if ofs.value > 0:
- if ofs_loc.is_imm():
- self.mc.ADD_ri(tmploc.value, tmploc.value, ofs_loc.value)
- else:
- self.mc.ADD_rr(tmploc.value, tmploc.value, ofs_loc.value)
- ofs_loc = tmploc
- self._load_from_mem(res_loc, base_loc, ofs_loc,
- imm(scale), signed, fcond)
- return fcond
-
- emit_op_getinteriorfield_gc_i = _genop_getinteriorfield
- emit_op_getinteriorfield_gc_r = _genop_getinteriorfield
- emit_op_getinteriorfield_gc_f = _genop_getinteriorfield
-
- def emit_op_setinteriorfield_gc(self, op, arglocs, regalloc, fcond):
- (base_loc, index_loc, value_loc,
- ofs_loc, ofs, itemsize, fieldsize) = arglocs
- scale = get_scale(fieldsize.value)
- tmploc, save = self.get_tmp_reg([base_loc, index_loc, value_loc,
ofs_loc])
- assert not save
- self.mc.gen_load_int(tmploc.value, itemsize.value)
- self.mc.MUL(tmploc.value, index_loc.value, tmploc.value)
- if ofs.value > 0:
- if ofs_loc.is_imm():
- self.mc.ADD_ri(tmploc.value, tmploc.value, ofs_loc.value)
- else:
- self.mc.ADD_rr(tmploc.value, tmploc.value, ofs_loc.value)
- self._write_to_mem(value_loc, base_loc, tmploc, imm(scale), fcond)
- return fcond
- emit_op_setinteriorfield_raw = emit_op_setinteriorfield_gc
-
- def emit_op_arraylen_gc(self, op, arglocs, regalloc, fcond):
- res, base_loc, ofs = arglocs
- self.load_reg(self.mc, res, base_loc, ofs.value)
- return fcond
-
- def emit_op_setarrayitem_gc(self, op, arglocs, regalloc, fcond):
- value_loc, base_loc, ofs_loc, scale, ofs = arglocs
- assert ofs_loc.is_core_reg()
- if scale.value > 0:
- self.mc.LSL_ri(r.ip.value, ofs_loc.value, scale.value)
- ofs_loc = r.ip
-
+ def emit_op_gc_store_indexed(self, op, arglocs, regalloc, fcond):
+ value_loc, base_loc, index_loc, size_loc, ofs_loc = arglocs
+ assert index_loc.is_core_reg()
# add the base offset
- if ofs.value > 0:
- self.mc.ADD_ri(r.ip.value, ofs_loc.value, imm=ofs.value)
- ofs_loc = r.ip
- self._write_to_mem(value_loc, base_loc, ofs_loc, scale, fcond)
+ if ofs_loc.value > 0:
+ self.mc.ADD_ri(r.ip.value, index_loc.value, imm=ofs_loc.value)
+ index_loc = r.ip
+ scale = get_scale(size_loc.value)
+ self._write_to_mem(value_loc, base_loc, index_loc, imm(scale), fcond)
return fcond
def _write_to_mem(self, value_loc, base_loc, ofs_loc, scale, fcond=c.AL):
+ # Write a value of size '1 << scale' at the address
+ # 'base_ofs + ofs_loc'. Note that 'scale' is not used to scale
+ # the offset!
if scale.value == 3:
assert value_loc.is_vfp_reg()
# vstr only supports imm offsets
@@ -789,43 +734,31 @@
else:
assert 0
- emit_op_setarrayitem_raw = emit_op_setarrayitem_gc
-
- def emit_op_raw_store(self, op, arglocs, regalloc, fcond):
- value_loc, base_loc, ofs_loc, scale, ofs = arglocs
- assert ofs_loc.is_core_reg()
- self._write_to_mem(value_loc, base_loc, ofs_loc, scale, fcond)
+ def _emit_op_gc_load_indexed(self, op, arglocs, regalloc, fcond):
+ res_loc, base_loc, index_loc, nsize_loc, ofs_loc = arglocs
+ assert index_loc.is_core_reg()
+ nsize = nsize_loc.value
+ signed = (nsize < 0)
+ # add the base offset
+ if ofs_loc.value > 0:
+ self.mc.ADD_ri(r.ip.value, index_loc.value, imm=ofs_loc.value)
+ index_loc = r.ip
+ #
+ scale = get_scale(abs(nsize))
+ self._load_from_mem(res_loc, base_loc, index_loc, imm(scale),
+ signed, fcond)
return fcond
- def _genop_getarrayitem(self, op, arglocs, regalloc, fcond):
- res_loc, base_loc, ofs_loc, scale, ofs = arglocs
- assert ofs_loc.is_core_reg()
- signed = op.getdescr().is_item_signed()
-
- # scale the offset as required
- # XXX we should try to encode the scale inside the "shift" part of LDR
- if scale.value > 0:
- self.mc.LSL_ri(r.ip.value, ofs_loc.value, scale.value)
- ofs_loc = r.ip
- # add the base offset
- if ofs.value > 0:
- self.mc.ADD_ri(r.ip.value, ofs_loc.value, imm=ofs.value)
- ofs_loc = r.ip
- #
- self._load_from_mem(res_loc, base_loc, ofs_loc, scale, signed, fcond)
- return fcond
-
- emit_op_getarrayitem_gc_i = _genop_getarrayitem
- emit_op_getarrayitem_gc_r = _genop_getarrayitem
- emit_op_getarrayitem_gc_f = _genop_getarrayitem
- emit_op_getarrayitem_gc_pure_i = _genop_getarrayitem
- emit_op_getarrayitem_gc_pure_r = _genop_getarrayitem
- emit_op_getarrayitem_gc_pure_f = _genop_getarrayitem
- emit_op_getarrayitem_raw_i = _genop_getarrayitem
- emit_op_getarrayitem_raw_f = _genop_getarrayitem
+ emit_op_gc_load_indexed_i = _emit_op_gc_load_indexed
+ emit_op_gc_load_indexed_r = _emit_op_gc_load_indexed
+ emit_op_gc_load_indexed_f = _emit_op_gc_load_indexed
def _load_from_mem(self, res_loc, base_loc, ofs_loc, scale,
signed=False, fcond=c.AL):
+ # Load a value of '1 << scale' bytes, from the memory location
+ # 'base_loc + ofs_loc'. Note that 'scale' is not used to scale
+ # the offset!
+ #
if scale.value == 3:
assert res_loc.is_vfp_reg()
# vldr only supports imm offsets
@@ -881,51 +814,6 @@
else:
assert 0
- def _genop_raw_load(self, op, arglocs, regalloc, fcond):
- res_loc, base_loc, ofs_loc, scale, ofs = arglocs
- assert ofs_loc.is_core_reg()
- # no base offset
- assert ofs.value == 0
- signed = op.getdescr().is_item_signed()
- self._load_from_mem(res_loc, base_loc, ofs_loc, scale, signed, fcond)
- return fcond
-
- emit_op_raw_load_i = _genop_raw_load
- emit_op_raw_load_f = _genop_raw_load
-
- def emit_op_strlen(self, op, arglocs, regalloc, fcond):
- l0, l1, res = arglocs
- if l1.is_imm():
- self.mc.LDR_ri(res.value, l0.value, l1.getint(), cond=fcond)
- else:
- self.mc.LDR_rr(res.value, l0.value, l1.value, cond=fcond)
- return fcond
-
- def emit_op_strgetitem(self, op, arglocs, regalloc, fcond):
- res, base_loc, ofs_loc, basesize = arglocs
- if ofs_loc.is_imm():
- self.mc.ADD_ri(r.ip.value, base_loc.value, ofs_loc.getint(),
- cond=fcond)
- else:
- self.mc.ADD_rr(r.ip.value, base_loc.value, ofs_loc.value,
- cond=fcond)
-
- self.mc.LDRB_ri(res.value, r.ip.value, basesize.value, cond=fcond)
- return fcond
-
- def emit_op_strsetitem(self, op, arglocs, regalloc, fcond):
- value_loc, base_loc, ofs_loc, basesize = arglocs
- if ofs_loc.is_imm():
- self.mc.ADD_ri(r.ip.value, base_loc.value, ofs_loc.getint(),
- cond=fcond)
- else:
- self.mc.ADD_rr(r.ip.value, base_loc.value, ofs_loc.value,
- cond=fcond)
-
- self.mc.STRB_ri(value_loc.value, r.ip.value, basesize.value,
- cond=fcond)
- return fcond
-
#from ../x86/regalloc.py:928 ff.
def emit_op_copystrcontent(self, op, arglocs, regalloc, fcond):
assert len(arglocs) == 0
@@ -1016,35 +904,6 @@
else:
raise AssertionError("bad unicode item size")
- emit_op_unicodelen = emit_op_strlen
-
- def emit_op_unicodegetitem(self, op, arglocs, regalloc, fcond):
- res, base_loc, ofs_loc, scale, basesize, itemsize = arglocs
- self.mc.ADD_rr(r.ip.value, base_loc.value, ofs_loc.value, cond=fcond,
- imm=scale.value, shifttype=shift.LSL)
- if scale.value == 2:
- self.mc.LDR_ri(res.value, r.ip.value, basesize.value, cond=fcond)
- elif scale.value == 1:
- self.mc.LDRH_ri(res.value, r.ip.value, basesize.value, cond=fcond)
- else:
- assert 0, itemsize.value
- return fcond
-
- def emit_op_unicodesetitem(self, op, arglocs, regalloc, fcond):
- value_loc, base_loc, ofs_loc, scale, basesize, itemsize = arglocs
- self.mc.ADD_rr(r.ip.value, base_loc.value, ofs_loc.value, cond=fcond,
- imm=scale.value, shifttype=shift.LSL)
- if scale.value == 2:
- self.mc.STR_ri(value_loc.value, r.ip.value, basesize.value,
- cond=fcond)
- elif scale.value == 1:
- self.mc.STRH_ri(value_loc.value, r.ip.value, basesize.value,
- cond=fcond)
- else:
- assert 0, itemsize.value
-
- return fcond
-
def store_force_descr(self, op, fail_locs, frame_depth):
pos = self.mc.currpos()
guard_token = self.build_guard_token(op, frame_depth, fail_locs, pos,
c.AL)
diff --git a/rpython/jit/backend/arm/regalloc.py
b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -34,9 +34,6 @@
from rpython.rtyper.lltypesystem import lltype, rffi, rstr, llmemory
from rpython.rtyper.lltypesystem.lloperation import llop
from rpython.jit.codewriter.effectinfo import EffectInfo
-from rpython.jit.backend.llsupport.descr import unpack_arraydescr
-from rpython.jit.backend.llsupport.descr import unpack_fielddescr
-from rpython.jit.backend.llsupport.descr import unpack_interiorfielddescr
from rpython.rlib.rarithmetic import r_uint
from rpython.jit.backend.llsupport.descr import CallDescr
@@ -802,15 +799,12 @@
src_locations2, dst_locations2, vfptmploc)
return []
- def prepare_op_setfield_gc(self, op, fcond):
+ def prepare_op_gc_store(self, op, fcond):
boxes = op.getarglist()
- ofs, size, sign = unpack_fielddescr(op.getdescr())
- return self._prepare_op_setfield(boxes, ofs, size)
-
- def _prepare_op_setfield(self, boxes, ofs, size):
- a0, a1 = boxes
- base_loc = self.make_sure_var_in_reg(a0, boxes)
- value_loc = self.make_sure_var_in_reg(a1, boxes)
+ base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
+ ofs = boxes[1].getint()
+ value_loc = self.make_sure_var_in_reg(boxes[2], boxes)
+ size = abs(boxes[3].getint())
ofs_size = default_imm_size if size < 8 else VMEM_imm_size
if check_imm_arg(ofs, size=ofs_size):
ofs_loc = imm(ofs)
@@ -819,19 +813,13 @@
self.assembler.load(ofs_loc, imm(ofs))
return [value_loc, base_loc, ofs_loc, imm(size)]
- prepare_op_setfield_raw = prepare_op_setfield_gc
-
- def prepare_op_zero_ptr_field(self, op, fcond):
+ def _prepare_op_gc_load(self, op, fcond):
a0 = op.getarg(0)
ofs = op.getarg(1).getint()
- return self._prepare_op_setfield([a0, ConstInt(0)], ofs, WORD)
-
- def _prepare_op_getfield(self, op, fcond):
- a0 = op.getarg(0)
- ofs, size, sign = unpack_fielddescr(op.getdescr())
+ nsize = op.getarg(2).getint() # negative for "signed"
base_loc = self.make_sure_var_in_reg(a0)
immofs = imm(ofs)
- ofs_size = default_imm_size if size < 8 else VMEM_imm_size
+ ofs_size = default_imm_size if abs(nsize) < 8 else VMEM_imm_size
if check_imm_arg(ofs, size=ofs_size):
ofs_loc = immofs
else:
@@ -839,17 +827,12 @@
self.assembler.load(ofs_loc, immofs)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
- res = self.force_allocate_reg(op)
- return [base_loc, ofs_loc, res, imm(size)]
+ res_loc = self.force_allocate_reg(op)
+ return [base_loc, ofs_loc, res_loc, imm(nsize)]
- prepare_op_getfield_gc_i = _prepare_op_getfield
- prepare_op_getfield_gc_r = _prepare_op_getfield
- prepare_op_getfield_gc_f = _prepare_op_getfield
- prepare_op_getfield_raw_i = _prepare_op_getfield
- prepare_op_getfield_raw_f = _prepare_op_getfield
- prepare_op_getfield_gc_pure_i = _prepare_op_getfield
- prepare_op_getfield_gc_pure_r = _prepare_op_getfield
- prepare_op_getfield_gc_pure_f = _prepare_op_getfield
+ prepare_op_gc_load_i = _prepare_op_gc_load
+ prepare_op_gc_load_r = _prepare_op_gc_load
+ prepare_op_gc_load_f = _prepare_op_gc_load
def prepare_op_increment_debug_counter(self, op, fcond):
boxes = op.getarglist()
@@ -859,188 +842,38 @@
self.free_temp_vars()
return [base_loc, value_loc]
- def _prepare_op_getinteriorfield(self, op, fcond):
- t = unpack_interiorfielddescr(op.getdescr())
- ofs, itemsize, fieldsize, sign = t
- args = op.getarglist()
- base_loc = self.make_sure_var_in_reg(op.getarg(0), args)
- index_loc = self.make_sure_var_in_reg(op.getarg(1), args)
- immofs = imm(ofs)
- ofs_size = default_imm_size if fieldsize < 8 else VMEM_imm_size
- if check_imm_arg(ofs, size=ofs_size):
- ofs_loc = immofs
- else:
- ofs_loc = self.get_scratch_reg(INT, args)
- self.assembler.load(ofs_loc, immofs)
+ def prepare_op_gc_store_indexed(self, op, fcond):
+ boxes = op.getarglist()
+ base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
+ value_loc = self.make_sure_var_in_reg(boxes[2], boxes)
+ index_loc = self.make_sure_var_in_reg(boxes[1], boxes)
+ assert boxes[3].getint() == 1 # scale
+ ofs = boxes[4].getint()
+ size = abs(boxes[5].getint())
+ assert check_imm_arg(ofs)
+ return [value_loc, base_loc, index_loc, imm(size), imm(ofs)]
+
+ def _prepare_op_gc_load_indexed(self, op, fcond):
+ boxes = op.getarglist()
+ base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
+ index_loc = self.make_sure_var_in_reg(boxes[1], boxes)
+ assert boxes[2].getint() == 1 # scale
+ ofs = boxes[3].getint()
+ nsize = boxes[4].getint()
+ assert check_imm_arg(ofs)
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
- result_loc = self.force_allocate_reg(op)
- return [base_loc, index_loc, result_loc, ofs_loc, imm(ofs),
- imm(itemsize), imm(fieldsize)]
+ res_loc = self.force_allocate_reg(op)
+ return [res_loc, base_loc, index_loc, imm(nsize), imm(ofs)]
- prepare_op_getinteriorfield_gc_i = _prepare_op_getinteriorfield
- prepare_op_getinteriorfield_gc_r = _prepare_op_getinteriorfield
- prepare_op_getinteriorfield_gc_f = _prepare_op_getinteriorfield
-
- def prepare_op_setinteriorfield_gc(self, op, fcond):
- t = unpack_interiorfielddescr(op.getdescr())
- ofs, itemsize, fieldsize, sign = t
- args = op.getarglist()
- base_loc = self.make_sure_var_in_reg(op.getarg(0), args)
- index_loc = self.make_sure_var_in_reg(op.getarg(1), args)
- value_loc = self.make_sure_var_in_reg(op.getarg(2), args)
- immofs = imm(ofs)
- ofs_size = default_imm_size if fieldsize < 8 else VMEM_imm_size
- if check_imm_arg(ofs, size=ofs_size):
- ofs_loc = immofs
- else:
- ofs_loc = self.get_scratch_reg(INT, args)
- self.assembler.load(ofs_loc, immofs)
- return [base_loc, index_loc, value_loc, ofs_loc, imm(ofs),
- imm(itemsize), imm(fieldsize)]
- prepare_op_setinteriorfield_raw = prepare_op_setinteriorfield_gc
-
- def prepare_op_arraylen_gc(self, op, fcond):
- arraydescr = op.getdescr()
- assert isinstance(arraydescr, ArrayDescr)
- ofs = arraydescr.lendescr.offset
- arg = op.getarg(0)
- base_loc = self.make_sure_var_in_reg(arg)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op)
- return [res, base_loc, imm(ofs)]
-
- def prepare_op_setarrayitem_gc(self, op, fcond):
- size, ofs, _ = unpack_arraydescr(op.getdescr())
- scale = get_scale(size)
- args = op.getarglist()
- base_loc = self.make_sure_var_in_reg(args[0], args)
- value_loc = self.make_sure_var_in_reg(args[2], args)
- ofs_loc = self.make_sure_var_in_reg(args[1], args)
- assert check_imm_arg(ofs)
- return [value_loc, base_loc, ofs_loc, imm(scale), imm(ofs)]
- prepare_op_setarrayitem_raw = prepare_op_setarrayitem_gc
- prepare_op_raw_store = prepare_op_setarrayitem_gc
-
- def _prepare_op_getarrayitem(self, op, fcond):
- boxes = op.getarglist()
- size, ofs, _ = unpack_arraydescr(op.getdescr())
- scale = get_scale(size)
- base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
- ofs_loc = self.make_sure_var_in_reg(boxes[1], boxes)
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op)
- assert check_imm_arg(ofs)
- return [res, base_loc, ofs_loc, imm(scale), imm(ofs)]
-
- prepare_op_getarrayitem_gc_i = _prepare_op_getarrayitem
- prepare_op_getarrayitem_gc_r = _prepare_op_getarrayitem
- prepare_op_getarrayitem_gc_f = _prepare_op_getarrayitem
- prepare_op_getarrayitem_raw_i = _prepare_op_getarrayitem
- prepare_op_getarrayitem_raw_f = _prepare_op_getarrayitem
- prepare_op_getarrayitem_gc_pure_i = _prepare_op_getarrayitem
- prepare_op_getarrayitem_gc_pure_r = _prepare_op_getarrayitem
- prepare_op_getarrayitem_gc_pure_f = _prepare_op_getarrayitem
- prepare_op_raw_load_i = _prepare_op_getarrayitem
- prepare_op_raw_load_f = _prepare_op_getarrayitem
-
- def prepare_op_strlen(self, op, fcond):
- args = op.getarglist()
- l0 = self.make_sure_var_in_reg(op.getarg(0))
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
- self.cpu.translate_support_code)
- immofs = imm(ofs_length)
- if check_imm_arg(ofs_length):
- l1 = immofs
- else:
- l1 = self.get_scratch_reg(INT, args)
- self.assembler.load(l1, immofs)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
-
- res = self.force_allocate_reg(op)
- self.possibly_free_var(op)
- return [l0, l1, res]
-
- def prepare_op_strgetitem(self, op, fcond):
- boxes = op.getarglist()
- base_loc = self.make_sure_var_in_reg(boxes[0])
-
- a1 = boxes[1]
- imm_a1 = check_imm_box(a1)
- if imm_a1:
- ofs_loc = self.convert_to_imm(a1)
- else:
- ofs_loc = self.make_sure_var_in_reg(a1, boxes)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op)
-
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
- self.cpu.translate_support_code)
- assert itemsize == 1
- return [res, base_loc, ofs_loc, imm(basesize)]
-
- def prepare_op_strsetitem(self, op, fcond):
- boxes = op.getarglist()
- base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
- ofs_loc = self.make_sure_var_in_reg(boxes[1], boxes)
- value_loc = self.make_sure_var_in_reg(boxes[2], boxes)
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
- self.cpu.translate_support_code)
- assert itemsize == 1
- return [value_loc, base_loc, ofs_loc, imm(basesize)]
+ prepare_op_gc_load_indexed_i = _prepare_op_gc_load_indexed
+ prepare_op_gc_load_indexed_r = _prepare_op_gc_load_indexed
+ prepare_op_gc_load_indexed_f = _prepare_op_gc_load_indexed
prepare_op_copystrcontent = void
prepare_op_copyunicodecontent = void
prepare_op_zero_array = void
- def prepare_op_unicodelen(self, op, fcond):
- l0 = self.make_sure_var_in_reg(op.getarg(0))
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
- self.cpu.translate_support_code)
- immofs = imm(ofs_length)
- if check_imm_arg(ofs_length):
- l1 = immofs
- else:
- l1 = self.get_scratch_reg(INT, [op.getarg(0)])
- self.assembler.load(l1, immofs)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op)
- return [l0, l1, res]
-
- def prepare_op_unicodegetitem(self, op, fcond):
- boxes = op.getarglist()
- base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
- ofs_loc = self.make_sure_var_in_reg(boxes[1], boxes)
-
- self.possibly_free_vars_for_op(op)
- self.free_temp_vars()
- res = self.force_allocate_reg(op)
-
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
- self.cpu.translate_support_code)
- scale = itemsize / 2
- return [res, base_loc, ofs_loc,
- imm(scale), imm(basesize), imm(itemsize)]
-
- def prepare_op_unicodesetitem(self, op, fcond):
- boxes = op.getarglist()
- base_loc = self.make_sure_var_in_reg(boxes[0], boxes)
- ofs_loc = self.make_sure_var_in_reg(boxes[1], boxes)
- value_loc = self.make_sure_var_in_reg(boxes[2], boxes)
- basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
- self.cpu.translate_support_code)
- scale = itemsize / 2
- return [value_loc, base_loc, ofs_loc,
- imm(scale), imm(basesize), imm(itemsize)]
-
def _prepare_op_same_as(self, op, fcond):
arg = op.getarg(0)
imm_arg = check_imm_box(arg)
@@ -1142,8 +975,7 @@
def prepare_op_cond_call_gc_wb(self, op, fcond):
# we force all arguments in a reg because it will be needed anyway by
- # the following setfield_gc or setarrayitem_gc. It avoids loading it
- # twice from the memory.
+ # the following gc_store. It avoids loading it twice from the memory.
N = op.numargs()
args = op.getarglist()
arglocs = [self.make_sure_var_in_reg(op.getarg(i), args)
diff --git a/rpython/jit/backend/arm/runner.py
b/rpython/jit/backend/arm/runner.py
--- a/rpython/jit/backend/arm/runner.py
+++ b/rpython/jit/backend/arm/runner.py
@@ -29,6 +29,10 @@
float_regs = VFPRegisterManager.all_regs
frame_reg = fp
+ # can an ISA instruction handle a factor to the offset?
+ # XXX should be: tuple(1 << i for i in range(31))
+ load_supported_factors = (1,)
+
def __init__(self, rtyper, stats, opts=None, translate_support_code=False,
gcdescr=None):
AbstractLLCPU.__init__(self, rtyper, stats, opts,
_______________________________________________
pypy-commit mailing list
[email protected]
https://mail.python.org/mailman/listinfo/pypy-commit
