Author: Richard Plangger <planri...@gmail.com> Branch: memop-simplify3 Changeset: r81452:eb4a9cb58507 Date: 2015-12-28 13:11 +0100 http://bitbucket.org/pypy/pypy/changeset/eb4a9cb58507/
Log: removed _get_interiorfield_addr method and moved a stripped down version to the regalloc class diff --git a/rpython/jit/backend/test/runner_test.py b/rpython/jit/backend/test/runner_test.py --- a/rpython/jit/backend/test/runner_test.py +++ b/rpython/jit/backend/test/runner_test.py @@ -5033,7 +5033,6 @@ lengthbox, scale, offset) if v_len is None: v_len = ConstInt(e_offset) - #import pdb; pdb.set_trace() args = [InputArgRef(a_ref), v_start, v_len, ConstInt(scale_start), ConstInt(scale_len)] ops.append(ResOperation(rop.ZERO_ARRAY, args, diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py --- a/rpython/jit/backend/x86/assembler.py +++ b/rpython/jit/backend/x86/assembler.py @@ -1528,20 +1528,6 @@ # return shift - def _get_interiorfield_addr(self, temp_loc, index_loc, itemsize_loc, - base_loc, ofs_loc): - assert isinstance(itemsize_loc, ImmedLoc) - itemsize = itemsize_loc.value - if isinstance(index_loc, ImmedLoc): - temp_loc = imm(index_loc.value * itemsize) - shift = 0 - else: - assert valid_addressing_size(itemsize), "rewrite did not correctly handle shift/mul!" - temp_loc = index_loc - shift = get_scale(itemsize) - assert isinstance(ofs_loc, ImmedLoc) - return AddressLoc(base_loc, temp_loc, shift, ofs_loc.value) - def genop_discard_increment_debug_counter(self, op, arglocs): # The argument should be an immediate address. This should # generate code equivalent to a GETFIELD_RAW, an ADD(1), and a @@ -2368,12 +2354,13 @@ jmp_adr0 = self.mc.get_relative_pos() self.mc.MOV(eax, heap(nursery_free_adr)) - if valid_addressing_size(itemsize): - shift = get_scale(itemsize) - else: - shift = self._imul_const_scaled(self.mc, edi.value, - varsizeloc.value, itemsize) - varsizeloc = edi + assert valid_addressing_size(itemsize) + shift = get_scale(itemsize) + #else: + # shift = self._imul_const_scaled(self.mc, edi.value, + # varsizeloc.value, itemsize) + # varsizeloc = edi + # now varsizeloc is a register != eax. The size of # the variable part of the array is (varsizeloc << shift) assert arraydescr.basesize >= self.gc_minimal_size_in_nursery diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py --- a/rpython/jit/backend/x86/regalloc.py +++ b/rpython/jit/backend/x86/regalloc.py @@ -9,7 +9,7 @@ from rpython.jit.backend.llsupport.gcmap import allocate_gcmap from rpython.jit.backend.llsupport.regalloc import (FrameManager, BaseRegalloc, RegisterManager, TempVar, compute_vars_longevity, is_comparison_or_ovf_op, - valid_addressing_size) + valid_addressing_size, get_scale) from rpython.jit.backend.x86 import rx86 from rpython.jit.backend.x86.arch import (WORD, JITFRAME_FIXED_SIZE, IS_X86_32, IS_X86_64, DEFAULT_FRAME_BYTES) @@ -32,6 +32,7 @@ from rpython.rtyper.annlowlevel import cast_instance_to_gcref from rpython.rtyper.lltypesystem import lltype, rffi, rstr from rpython.rtyper.lltypesystem.lloperation import llop +from rpython.jit.backend.x86.regloc import AddressLoc class X86RegisterManager(RegisterManager): @@ -1389,6 +1390,20 @@ def consider_keepalive(self, op): pass + def _scaled_addr(self, index_loc, itemsize_loc, + base_loc, ofs_loc): + assert isinstance(itemsize_loc, ImmedLoc) + itemsize = itemsize_loc.value + if isinstance(index_loc, ImmedLoc): + temp_loc = imm(index_loc.value * itemsize) + shift = 0 + else: + assert valid_addressing_size(itemsize), "rewrite did not correctly handle shift/mul!" + temp_loc = index_loc + shift = get_scale(itemsize) + assert isinstance(ofs_loc, ImmedLoc) + return AddressLoc(base_loc, temp_loc, shift, ofs_loc.value) + def consider_zero_array(self, op): _, baseofs, _ = unpack_arraydescr(op.getdescr()) length_box = op.getarg(2) @@ -1423,13 +1438,11 @@ # address that we will pass as first argument to memset(). # It can be in the same register as either one, but not in # args[2], because we're still needing the latter. - #import pdb; pdb.set_trace() dstaddr_box = TempVar() dstaddr_loc = self.rm.force_allocate_reg(dstaddr_box, [args[2]]) itemsize_loc = imm(start_itemsize) - dst_addr = self.assembler._get_interiorfield_addr( - dstaddr_loc, startindex_loc, itemsize_loc, - base_loc, imm(baseofs)) + dst_addr = self._scaled_addr(startindex_loc, itemsize_loc, + base_loc, imm(baseofs)) self.assembler.mc.LEA(dstaddr_loc, dst_addr) # if constbytes >= 0: @@ -1446,8 +1459,7 @@ bytes_loc = self.rm.force_allocate_reg(bytes_box, [dstaddr_box]) len_itemsize_loc = imm(len_itemsize) - b_adr = self.assembler._get_interiorfield_addr( - bytes_loc, length_loc, len_itemsize_loc, imm0, imm0) + b_adr = self._scaled_addr(length_loc, len_itemsize_loc, imm0, imm0) self.assembler.mc.LEA(bytes_loc, b_adr) length_box = bytes_box length_loc = bytes_loc diff --git a/rpython/jit/backend/x86/vector_ext.py b/rpython/jit/backend/x86/vector_ext.py --- a/rpython/jit/backend/x86/vector_ext.py +++ b/rpython/jit/backend/x86/vector_ext.py @@ -9,7 +9,7 @@ ebp, r8, r9, r10, r11, r12, r13, r14, r15, xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, X86_64_SCRATCH_REG, X86_64_XMM_SCRATCH_REG, AddressLoc) -from rpython.jit.backend.llsupport.regalloc import (get_scale, valid_addressing_size) +from rpython.jit.backend.llsupport.regalloc import get_scale from rpython.jit.metainterp.resoperation import (rop, ResOperation, VectorOp, VectorGuardOp) from rpython.rlib.objectmodel import we_are_translated _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit