Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r81523:72ff734c842f
Date: 2016-01-02 10:55 +0100
http://bitbucket.org/pypy/pypy/changeset/72ff734c842f/
Log: asmlen test failed, because more instructions in the entry of a
bridge are now compiled (realloc check), seems about right what
other backends implement!
diff --git a/rpython/jit/backend/zarch/test/test_runner.py
b/rpython/jit/backend/zarch/test/test_runner.py
--- a/rpython/jit/backend/zarch/test/test_runner.py
+++ b/rpython/jit/backend/zarch/test/test_runner.py
@@ -24,6 +24,6 @@
cpu.setup_once()
return cpu
- # TODO verify: the lgr might be redundant!
add_loop_instructions = "lg; lgr; larl; agr; cgfi; je; j;$"
- bridge_loop_instructions = ("larl; lg; br;")
+ bridge_loop_instructions = "larl; lg; cgfi; je; lghi; stg; " \
+ "lay; lgfi; lgfi; basr; lay; lg; br;$"
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