Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r81829:8c4d49ec746f
Date: 2016-01-18 09:13 +0100
http://bitbucket.org/pypy/pypy/changeset/8c4d49ec746f/
Log: dict comprehension rewrite to loop overwrote parameter variable of
the function
diff --git a/rpython/jit/backend/test/zll_stress.py
b/rpython/jit/backend/test/zll_stress.py
--- a/rpython/jit/backend/test/zll_stress.py
+++ b/rpython/jit/backend/test/zll_stress.py
@@ -19,5 +19,4 @@
r = Random()
r.jumpahead(piece*99999999)
for i in range(piece*per_piece, (piece+1)*per_piece):
- print " i = %d; r.setstate(%s)" % (i, r.getstate())
check_random_function(cpu, LLtypeOperationBuilder, r, i,
total_iterations)
diff --git a/rpython/jit/backend/zarch/regalloc.py
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -195,6 +195,10 @@
if even.is_even():
# found an even registers that is actually free
odd = REGS[even.value+1]
+ if odd not in r.MANAGED_REGS:
+ # makes no sense to use this register!
+ i -= 1
+ continue
if odd not in self.free_regs:
# sadly odd is not free, but for spilling
# we found a candidate
@@ -215,7 +219,11 @@
# a candidate?
odd = even
even = REGS[odd.value-1]
- if even in r.MANAGED_REGS and even not in self.free_regs:
+ if even not in r.MANAGED_REGS:
+ # makes no sense to use this register!
+ i -= 1
+ continue
+ if even not in self.free_regs:
# yes even might be a candidate
# this means that odd is free, but not even
candidates[even] = True
@@ -267,8 +275,8 @@
# require one spill, thus we need to spill two!
# this is a rare case!
reverse_mapping = {}
- for var, reg in self.reg_bindings.items():
- reverse_mapping[reg] = var
+ for v, reg in self.reg_bindings.items():
+ reverse_mapping[reg] = v
# always take the first
for i, reg in enumerate(r.MANAGED_REGS):
if i % 2 == 1:
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