[pypy-commit] pypy s390x-backend: it can happen that longevity does not contain an entry for an operation (e.g. int_mul_ovf and result is not used), then when trying to spill a variable op can be in reg_bindings, but is not in longevity -> KeyError,

[plan_rich]

Author: Richard Plangger <planri...@gmail.com>
Branch: s390x-backend
Changeset: r81885:7ac200cdeecd
Date: 2016-01-21 11:24 +0100
http://bitbucket.org/pypy/pypy/changeset/7ac200cdeecd/

Log:    it can happen that longevity does not contain an entry for an
        operation (e.g. int_mul_ovf and result is not used), then when
        trying to spill a variable op can be in reg_bindings, but is not in
        longevity -> KeyError, fixed this by ensuring that the pair
        allocation happens at the latest point in the regalloc step

diff --git a/rpython/jit/backend/zarch/helper/regalloc.py 
b/rpython/jit/backend/zarch/helper/regalloc.py
--- a/rpython/jit/backend/zarch/helper/regalloc.py
+++ b/rpython/jit/backend/zarch/helper/regalloc.py
@@ -51,11 +51,11 @@
     a1 = op.getarg(1)
     if a0.is_constant():
         a0, a1 = a1, a0
-    lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=False)
     if check_imm32(a1):
         l1 = imm(a1.getint())
     else:
         l1 = self.ensure_reg(a1)
+    lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=False)
     self.free_op_vars()
     return [lr, lq, l1]
 
@@ -63,15 +63,14 @@
     def f(self, op):
         a0 = op.getarg(0)
         a1 = op.getarg(1)
+        l1 = self.ensure_reg(a1)
         if isinstance(a0, Const):
             poolloc = self.ensure_reg(a0)
             lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=modulus, 
must_exist=False)
             self.assembler.mc.LG(lq, poolloc)
         else:
             lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=modulus)
-        l1 = self.ensure_reg(a1)
         self.free_op_vars()
-        self.rm._check_invariants()
         return [lr, lq, l1]
     return f
 
diff --git a/rpython/jit/backend/zarch/regalloc.py 
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -952,19 +952,19 @@
 
     def prepare_zero_array(self, op):
         itemsize, ofs, _ = unpack_arraydescr(op.getdescr())
+        startindex_loc = self.ensure_reg_or_16bit_imm(op.getarg(1))
+        tempvar = TempInt()
+        self.rm.temp_boxes.append(tempvar)
+        ofs_loc = self.ensure_reg_or_16bit_imm(ConstInt(ofs))
+        pad_byte, _ = self.rm.ensure_even_odd_pair(tempvar, tempvar,
+                              bind_first=True, must_exist=False, 
move_regs=False)
         base_loc, length_loc = self.rm.ensure_even_odd_pair(op.getarg(0), op,
               bind_first=True, must_exist=False, load_loc_odd=False)
-        tempvar = TempInt()
-        self.rm.temp_boxes.append(tempvar)
-        pad_byte, _ = self.rm.ensure_even_odd_pair(tempvar, tempvar,
-                              bind_first=True, must_exist=False, 
move_regs=False)
-        startindex_loc = self.ensure_reg_or_16bit_imm(op.getarg(1))
 
         length_box = op.getarg(2)
         ll = self.rm.loc(length_box)
         if length_loc is not ll:
             self.assembler.regalloc_mov(ll, length_loc)
-        ofs_loc = self.ensure_reg_or_16bit_imm(ConstInt(ofs))
         return [base_loc, startindex_loc, length_loc, ofs_loc, imm(itemsize), 
pad_byte]
 
     def prepare_cond_call(self, op):
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