Author: Richard Plangger <planri...@gmail.com>
Branch: s390x-backend
Changeset: r82067:71aa29c678e8
Date: 2016-02-04 08:44 +0100
http://bitbucket.org/pypy/pypy/changeset/71aa29c678e8/

Log:    proper fix for the volatile reg. provided to gc write barrier array

diff --git a/rpython/jit/backend/zarch/opassembler.py 
b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -527,9 +527,21 @@
         if not is_frame:
             mc.LGR(r.r0, loc_base)    # unusual argument location
 
+        loc_index = arglocs[1]
+        # loc_index may be in r2 to r5.
+        # the wb_slow_path may trash these registers
+
+        if loc_index.is_reg() and loc_index.value < 6:
+            mc.LAY(r.SP, l.addr(-WORD, r.SP))
+            mc.STG(loc_index, l.addr(0, r.SP))
+
         mc.load_imm(r.r14, self.wb_slowpath[helper_num])
         mc.BASR(r.r14, r.r14)
 
+        if loc_index.is_reg() and loc_index.value < 6:
+            mc.LG(loc_index, l.addr(0, r.SP))
+            mc.LAY(r.SP, l.addr(WORD, r.SP))
+
         if card_marking_mask:
             # The helper ends again with a check of the flag in the object.
             # So here, we can simply write again a beq, which will be
@@ -545,10 +557,7 @@
             #
             # case GCFLAG_CARDS_SET: emit a few instructions to do
             # directly the card flag setting
-            loc_index = arglocs[1]
             if loc_index.is_reg():
-                # must a register that is preserved across function calls
-                assert loc_index.value >= 6
                 tmp_loc = arglocs[2]
                 n = descr.jit_wb_card_page_shift
 
diff --git a/rpython/jit/backend/zarch/regalloc.py 
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -984,11 +984,8 @@
         return arglocs
 
     def prepare_cond_call_gc_wb_array(self, op):
-        # just calling ensure_reg may return a register r2->r6.
-        # but in the assembly a sub routine is called that trashes r2->r6.
-        # thus select two registers that are preserved
         arglocs = [self.ensure_reg(op.getarg(0), force_in_reg=True),
-                   self.ensure_reg_or_16bit_imm(op.getarg(1), 
selected_reg=r.r7),
+                   self.ensure_reg_or_16bit_imm(op.getarg(1)),
                    None]
         if arglocs[1].is_reg():
             arglocs[2] = self.get_scratch_reg(INT)
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