[pypy-commit] pypy regalloc: (remi, plan_rich) work in progress

[plan_rich]

Author: Richard Plangger <planri...@gmail.com>
Branch: regalloc
Changeset: r82423:f8ee5bddeb4b
Date: 2016-02-23 11:53 +0100
http://bitbucket.org/pypy/pypy/changeset/f8ee5bddeb4b/

Log:    (remi, plan_rich) work in progress

diff --git a/rpython/jit/backend/llsupport/test/test_regalloc_call.py 
b/rpython/jit/backend/llsupport/test/test_regalloc_call.py
--- a/rpython/jit/backend/llsupport/test/test_regalloc_call.py
+++ b/rpython/jit/backend/llsupport/test/test_regalloc_call.py
@@ -1,5 +1,6 @@
 from rpython.jit.tool.oparser import parse
 from rpython.jit.backend.x86.regalloc import RegAlloc
+from rpython.jit.backend.x86.regloc import REGLOCS
 from rpython.jit.backend.detect_cpu import getcpuclass
 from rpython.jit.backend.x86.arch import DEFAULT_FRAME_BYTES
 from rpython.jit.metainterp.history import TargetToken
@@ -11,7 +12,9 @@
     def __repr__(self):
         return 'r%d' % self.n
 
-r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 = [FakeReg(i) for i in range(1,11)]
+eax, ecx, edx, ebx, esp, ebp, esi, edi, r8, r9, r10, r11, r12, r13, r14, r15 = 
REGLOCS
+caller_saved = []
+callee_saved = []
 
 CPU = getcpuclass()
 
@@ -19,12 +22,11 @@
     ops = parse(text)
     tt = None
     tt = TargetToken(ops.operations[-1].getdescr())
-    ops.operations = [ResOperation(rop.LABEL, ops.inputargs, None, descr=tt)] 
+ ops.operations
     for op in ops.operations:
         if op.getopnum() == rop.JUMP:
             assert tt is not None
             op.setdescr(tt)
-    return ops
+    return tt, ops
 
 class FakeMachineCodeBuilder(object):
     _frame_size = DEFAULT_FRAME_BYTES
@@ -46,7 +48,10 @@
 CPURegalloc = RegAlloc
 class FakeRegAlloc(CPURegalloc):
     def __init__(self, tracealloc, caller_saved, callee_saved):
+        self.caller_saved = caller_saved
+        self.callee_saved = callee_saved
         self.all_regs = callee_saved[:] + callee_saved
+        self.free_regs = callee_saved[:] + callee_saved
         CPURegalloc.__init__(self, FakeAssembler(), False)
         self.tracealloc = tracealloc
         self.steps = set()
@@ -65,16 +70,28 @@
         self.compiled_loop_token = None
 
 class TraceAllocation(object):
-    def __init__(self, trace, caller_saved, callee_saved, binding):
+    def __init__(self, trace, caller_saved, callee_saved, binding, tt):
         self.trace = trace
         self.regalloc = FakeRegAlloc(self, caller_saved, callee_saved)
-        self.initial_binding = binding
+        self.initial_binding = { str(var): reg for var, reg in 
zip(trace.inputargs, binding) }
         looptoken = FakeLoopToken()
         gcrefs = None
+        tt._x86_arglocs = binding
+
         for op in trace.operations:
             for arg in op.getarglist():
                 pass
         self.regalloc.prepare_loop(self.trace.inputargs, 
self.trace.operations, looptoken, gcrefs)
+
+
+        for var, reg in zip(trace.inputargs, binding):
+            self.regalloc.rm.reg_bindings[var] = reg
+        fr = self.regalloc.rm.free_regs
+        self.regalloc.rm.free_regs = [reg for reg in fr if reg not in binding]
+
+        self.regalloc.rm.all_regs = self.regalloc.all_regs
+        self.regalloc.rm.save_around_call_regs = self.regalloc.caller_saved
+
         self.regalloc.walk_operations(trace.inputargs, trace.operations)
 
     def initial_register(self, name):
@@ -90,13 +107,13 @@
 class TestRegalloc(object):
 
     def test_allocate_register_into_jump_register(self):
-        ops = parse_loop("""
+        tt, ops = parse_loop("""
         [p0,i1]
         i2 = int_add(i1,i1)
         i3 = int_add(i2,i1)
         jump(p0,i2)
         """)
-        trace_alloc = TraceAllocation(ops, [r1, r2], [r3, r4], {'p0': r1, 
'i1': r2})
+        trace_alloc = TraceAllocation(ops, [eax, edx], [r8, r9], [eax, edx], 
tt)
         i2 = trace_alloc.initial_register('i2')
         i1 = trace_alloc.initial_register('i1')
         assert i2 == i1
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