[pypy-commit] pypy fix-longevity: (remi, plan_rich) lookup of initial binding works on this new branch

[plan_rich]

Author: Richard Plangger <planri...@gmail.com>
Branch: fix-longevity
Changeset: r82436:099af271b5bc
Date: 2016-02-23 14:13 +0100
http://bitbucket.org/pypy/pypy/changeset/099af271b5bc/

Log:    (remi, plan_rich) lookup of initial binding works on this new branch

diff --git a/rpython/jit/backend/llsupport/test/test_regalloc_call.py 
b/rpython/jit/backend/llsupport/test/test_regalloc_call.py
--- a/rpython/jit/backend/llsupport/test/test_regalloc_call.py
+++ b/rpython/jit/backend/llsupport/test/test_regalloc_call.py
@@ -4,7 +4,8 @@
 from rpython.jit.backend.detect_cpu import getcpuclass
 from rpython.jit.backend.x86.arch import DEFAULT_FRAME_BYTES
 from rpython.jit.metainterp.history import TargetToken
-from rpython.jit.metainterp.resoperation import rop, ResOperation
+from rpython.jit.metainterp.resoperation import (rop, ResOperation,
+        AbstractValue, CountingDict)
 
 class FakeReg(object):
     def __init__(self, i):
@@ -56,6 +57,7 @@
     def dump(self, *args): pass
     def regalloc_perform(self, *args): pass
     def regalloc_perform_guard(self, *args): pass
+    def guard_success_cc(self, *args): pass
     def label(self): pass
     def closing_jump(self, target): pass
 
@@ -88,14 +90,17 @@
     def __init__(self, trace, caller_saved, callee_saved, binding, tt):
         self.trace = trace
         self.regalloc = FakeRegAlloc(self, caller_saved, callee_saved)
-        self.initial_binding = { str(var): reg for var, reg in 
zip(trace.inputargs, binding) }
+        self.initial_binding = { var: reg for var, reg in zip(trace.inputargs, 
binding) }
         looptoken = FakeLoopToken()
         gcrefs = []
         tt._x86_arglocs = binding
 
+        AbstractValue._repr_memo = CountingDict()
         for op in trace.operations:
             for arg in op.getarglist():
+                arg.repr_short(arg._repr_memo)
                 pass
+            op.repr_short(op._repr_memo)
         self.regalloc.prepare_loop(self.trace.inputargs, 
self.trace.operations, looptoken, gcrefs)
 
         for var, reg in zip(trace.inputargs, binding):
@@ -108,8 +113,8 @@
 
         self.regalloc.walk_operations(trace.inputargs, trace.operations)
 
-    def initial_register(self, name):
-        return self.initial_binding.get(name, None)
+    def initial_register(self, var):
+        return self.initial_binding.get(var, None)
 
     def move_count(self):
         return len(self.regalloc.assembler.moves)
@@ -118,9 +123,8 @@
         bindings = self.regalloc.rm.reg_bindings
         print bindings
         for var in bindings:
-            varname = str(var)
-            if varname not in self.initial_binding:
-                self.initial_binding[varname] = bindings[var]
+            if var not in self.initial_binding:
+                self.initial_binding[var] = bindings[var]
 
 class TestRegalloc(object):
 
@@ -135,7 +139,7 @@
         i2 = trace_alloc.initial_register('i2')
         assert i2 == edx
 
-    def test_allocate_register_into_jump_register2(self):
+    def test_2allocate_register_into_jump_register2(self):
         tt, ops = parse_loop("""
         [p0,i1]
         i2 = int_add(i1,i1)
@@ -143,9 +147,9 @@
         guard_true(i3) []
         jump(p0,i2)
         """)
+        i2 = ops.operations[0]
+        i3 = ops.operations[1]
         trace_alloc = TraceAllocation(ops, [eax, edx], [r8, r9], [eax, edx], 
tt)
-        i2 = trace_alloc.initial_register('i2')
-        i3 = trace_alloc.initial_register('i3')
-        assert i2 == edx
-        assert i3 == r8
+        assert trace_alloc.initial_register(i2) == edx
+        assert trace_alloc.initial_register(i3) != edx
 
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