Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r82626:9fc4da160aeb
Date: 2016-03-01 09:56 +0100
http://bitbucket.org/pypy/pypy/changeset/9fc4da160aeb/
Log: RISBGN use RISBG (does alter the cc), changed parameter of
build_rie_f (signed to unsigned). removed some unnecessay asserts
(check now for each parameter)
diff --git a/rpython/jit/backend/zarch/assembler.py
b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -1158,8 +1158,6 @@
for reg in includes:
v = r.ALL_REG_INDEXES[reg]
offset = base_ofs + v * WORD
- assert offset >= 0
- assert offset <= 2**16-1
mc.STD(reg, l.addr(offset, r.SPP))
def _pop_fp_regs_from_jitframe(self, mc, includes=r.MANAGED_FP_REGS):
@@ -1167,8 +1165,6 @@
for reg in includes:
v = r.ALL_REG_INDEXES[reg]
offset = base_ofs + v * WORD
- assert offset >= 0
- assert offset <= 2**16-1
mc.LD(reg, l.addr(offset, r.SPP))
@@ -1399,7 +1395,7 @@
mc.AGHIK(r.RSZ, lengthloc, l.imm(constsize))
if force_realignment:
# "& ~(WORD-1)"
- mc.RISBGN(r.RSZ, r.RSZ, l.imm(0), l.imm(0x80 | 60), l.imm(0))
+ mc.RISBG(r.RSZ, r.RSZ, l.imm(0), l.imm(0x80 | 60), l.imm(0))
mc.AGRK(r.RSZ, r.RES, r.RSZ)
# now RSZ contains the total size in bytes, rounded up to a multiple
diff --git a/rpython/jit/backend/zarch/instruction_builder.py
b/rpython/jit/backend/zarch/instruction_builder.py
--- a/rpython/jit/backend/zarch/instruction_builder.py
+++ b/rpython/jit/backend/zarch/instruction_builder.py
@@ -341,7 +341,7 @@
return encode_rie_e
def build_rie_f(mnemonic, (opcode1,opcode2)):
- @builder.arguments('r,r,i8,i8,i8')
+ @builder.arguments('r,r,u8,u8,u8')
def encode_rie_f(self, reg1, reg2, i1, i2, i3):
self.writechar(opcode1)
byte = (reg1 & BIT_MASK_4) << 4 | (reg2 & BIT_MASK_4)
@@ -496,7 +496,6 @@
if type == 'h32':
value = arg.value
assert -2**31 <= value <= 2**31-1
- assert value & 0x1 == 0
@always_inline
def unpack_arg(arg, argtype):
check_arg_type(arg, argtype)
diff --git a/rpython/jit/backend/zarch/instructions.py
b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -42,11 +42,6 @@
'SLLG': ('rsy_a', ['\xEB','\x0D']),
# rotating
- # rotate, then insert selected bits
- # on the VM the miscellaneous-instruction-extensions
- # does not seem to be installed
- # cpu fails at this instruction, and gnu assembler
- # does not recognize mnemonic
'RISBG': ('rie_f', ['\xEC','\x55']),
'RISBGN': ('rie_f', ['\xEC','\x59']),
diff --git a/rpython/jit/backend/zarch/opassembler.py
b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -568,14 +568,13 @@
# compute in SCRATCH the index of the bit inside the byte:
# scratch = (index >> card_page_shift) & 7
# 0x80 sets zero flag. will store 0 into all not selected bits
- mc.RISBGN(r.SCRATCH, loc_index, l.imm(61), l.imm(0x80 | 63),
l.imm(64-n))
+ mc.RISBG(r.SCRATCH, loc_index, l.imm(61), l.imm(0x80 | 63),
l.imm(64-n))
mc.XG(tmp_loc, l.pool(self.pool.constant_64_ones))
# set SCRATCH2 to 1 << r1
mc.LGHI(r.SCRATCH2, l.imm(1))
mc.SLLG(r.SCRATCH2, r.SCRATCH2, l.addr(0,r.SCRATCH))
-
# set this bit inside the byte of interest
addr = l.addr(0, loc_base, tmp_loc)
mc.LLGC(r.SCRATCH, addr)
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