Author: Richard Plangger <[email protected]>
Branch: s390x-backend
Changeset: r82808:572470f1b45a
Date: 2016-03-06 11:57 +0100
http://bitbucket.org/pypy/pypy/changeset/572470f1b45a/
Log: reverted x86 assembler (malloc_cond_varsize), related to the issue
with bytesize and length
diff --git a/rpython/jit/backend/x86/assembler.py
b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1546,6 +1546,32 @@
genop_gc_load_indexed_r = _genop_gc_load_indexed
genop_gc_load_indexed_f = _genop_gc_load_indexed
+ def _imul_const_scaled(self, mc, targetreg, sourcereg, itemsize):
+ """Produce one operation to do roughly
+ targetreg = sourcereg * itemsize
+ except that the targetreg may still need shifting by 0,1,2,3.
+ """
+ if (itemsize & 7) == 0:
+ shift = 3
+ elif (itemsize & 3) == 0:
+ shift = 2
+ elif (itemsize & 1) == 0:
+ shift = 1
+ else:
+ shift = 0
+ itemsize >>= shift
+ #
+ if valid_addressing_size(itemsize - 1):
+ mc.LEA_ra(targetreg, (sourcereg, sourcereg,
+ get_scale(itemsize - 1), 0))
+ elif valid_addressing_size(itemsize):
+ mc.LEA_ra(targetreg, (rx86.NO_BASE_REGISTER, sourcereg,
+ get_scale(itemsize), 0))
+ else:
+ mc.IMUL_rri(targetreg, sourcereg, itemsize)
+ #
+ return shift
+
def genop_discard_increment_debug_counter(self, op, arglocs):
# The argument should be an immediate address. This should
# generate code equivalent to a GETFIELD_RAW, an ADD(1), and a
@@ -2374,8 +2400,12 @@
jmp_adr0 = self.mc.get_relative_pos()
self.mc.MOV(eax, heap(nursery_free_adr))
- assert valid_addressing_size(itemsize)
- shift = get_scale(itemsize)
+ if valid_addressing_size(itemsize):
+ shift = get_scale(itemsize)
+ else:
+ shift = self._imul_const_scaled(self.mc, edi.value,
+ varsizeloc.value, itemsize)
+ varsizeloc = edi
# now varsizeloc is a register != eax. The size of
# the variable part of the array is (varsizeloc << shift)
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