Author: Stefano Rivera <[email protected]>
Branch:
Changeset: r83227:f36e339f1a24
Date: 2016-03-21 14:25 -0400
http://bitbucket.org/pypy/pypy/changeset/f36e339f1a24/
Log: Indent proprocessor logic, for readability
diff --git a/rpython/rlib/rvmprof/src/vmprof_config.h
b/rpython/rlib/rvmprof/src/vmprof_config.h
--- a/rpython/rlib/rvmprof/src/vmprof_config.h
+++ b/rpython/rlib/rvmprof/src/vmprof_config.h
@@ -12,10 +12,10 @@
#define PC_FROM_UCONTEXT uc_mcontext->__ss.__rip
#endif
#elif defined(__arm__)
-#define PC_FROM_UCONTEXT uc_mcontext.arm_ip
+ #define PC_FROM_UCONTEXT uc_mcontext.arm_ip
#elif defined(__linux) && defined(__i386) && defined(__GNUC__)
-#define PC_FROM_UCONTEXT uc_mcontext.gregs[REG_EIP]
+ #define PC_FROM_UCONTEXT uc_mcontext.gregs[REG_EIP]
#else
-/* linux, gnuc */
-#define PC_FROM_UCONTEXT uc_mcontext.gregs[REG_RIP]
+ /* linux, gnuc */
+ #define PC_FROM_UCONTEXT uc_mcontext.gregs[REG_RIP]
#endif
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