Author: fijal
Branch:
Changeset: r83389:67480c50c1ab
Date: 2016-03-26 20:44 +0200
http://bitbucket.org/pypy/pypy/changeset/67480c50c1ab/
Log: the most obvious fix on arm
diff --git a/rpython/jit/backend/arm/assembler.py
b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -939,9 +939,9 @@
op = operations[i]
self.mc.mark_op(op)
opnum = op.getopnum()
- if op.has_no_side_effect() and op not in regalloc.longevity:
+ if rop.has_no_side_effect(opnum) and op not in regalloc.longevity:
regalloc.possibly_free_vars_for_op(op)
- elif not we_are_translated() and op.getopnum() == -127:
+ elif not we_are_translated() and op.getopnum() == rop.FORCE_SPILL:
regalloc.prepare_force_spill(op, fcond)
else:
arglocs = regalloc_operations[opnum](regalloc, op, fcond)
@@ -949,7 +949,7 @@
fcond = asm_operations[opnum](self, op, arglocs,
regalloc, fcond)
assert fcond is not None
- if op.is_guard():
+ if rop.is_guard(opnum):
regalloc.possibly_free_vars(op.getfailargs())
if op.type != 'v':
regalloc.possibly_free_var(op)
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