Author: Richard Plangger <[email protected]>
Branch: ppc-vsx-support
Changeset: r85159:9072f071d260
Date: 2016-06-14 14:47 +0200
http://bitbucket.org/pypy/pypy/changeset/9072f071d260/
Log: added vector store instruction and test for a load store combination
diff --git a/rpython/jit/backend/ppc/codebuilder.py
b/rpython/jit/backend/ppc/codebuilder.py
--- a/rpython/jit/backend/ppc/codebuilder.py
+++ b/rpython/jit/backend/ppc/codebuilder.py
@@ -268,7 +268,6 @@
lwbrx = XD(31, XO1=534)
lwzux = XD(31, XO1=55)
lwzx = XD(31, XO1=23)
- lxvd2x = XX1(31, XO1=844)
mcrfs = Form("crfD", "crfS", "XO1")(63, XO1=64)
mcrxr = Form("crfD", "XO1")(31, XO1=512)
@@ -571,7 +570,21 @@
xor = XS(31, XO1=316, Rc=0)
xorx = XS(31, XO1=316, Rc=1)
-class PPCAssembler(BasicPPCAssembler):
+ #
+
+class PPCVSXAssembler(object):
+ _mixin_ = True
+
+ # load
+ lxvdsx = XX1(31, XO1=332) # splat first element
+ lxvd2x = XX1(31, XO1=844)
+ lxvw4x = XX1(31, XO1=780)
+
+ # store
+ stxvd2x = XX1(31, XO1=972)
+ stxvw4x = XX1(31, XO1=908)
+
+class PPCAssembler(BasicPPCAssembler, PPCVSXAssembler):
BA = BasicPPCAssembler
# awkward mnemonics:
diff --git a/rpython/jit/backend/ppc/test/test_vector_instr.py
b/rpython/jit/backend/ppc/test/test_vector_instr.py
--- a/rpython/jit/backend/ppc/test/test_vector_instr.py
+++ b/rpython/jit/backend/ppc/test/test_vector_instr.py
@@ -58,10 +58,19 @@
if cpu not in ["ppc", "ppc64", "ppc-64"]:
py.test.skip("can't test all of ppcgen on non-PPC!")
- @vec_asmtest(memory=[(8, signed, [0,0])])
+ @vec_asmtest(memory=[(16, signed, [0,0])])
def test_unaligned_load(self, a, mem):
a.load_imm(r15, mem)
a.lxvd2x(vr0.value, 0, r15.value)
a.blr()
return [ (0, signed, mem), (0, signed, mem+8) ]
+ @vec_asmtest(memory=[(16, signed, [1,2]), (16, signed, [0,0])])
+ def test_unaligned_load_and_store(self, a, mem_l, mem_t):
+ a.load_imm(r15, mem_l)
+ a.load_imm(r14, mem_t)
+ a.lxvd2x(vr0.value, 0, r15.value)
+ a.stxvd2x(vr0.value, 0, r14.value)
+ a.blr()
+ return [ (1, signed, mem_t), (2, signed, mem_t+8) ]
+
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