Author: Richard Plangger <[email protected]>
Branch: ppc-vsx-support
Changeset: r85179:fcd54f26d4ff
Date: 2016-06-15 16:02 +0200
http://bitbucket.org/pypy/pypy/changeset/fcd54f26d4ff/
Log: a new vector register managed, starting to impl. regalloc for loads
diff --git a/rpython/jit/backend/ppc/opassembler.py
b/rpython/jit/backend/ppc/opassembler.py
--- a/rpython/jit/backend/ppc/opassembler.py
+++ b/rpython/jit/backend/ppc/opassembler.py
@@ -29,6 +29,7 @@
from rpython.jit.codewriter.effectinfo import EffectInfo
from rpython.jit.backend.ppc import callbuilder
from rpython.rlib.rarithmetic import r_uint
+from rpython.jit.backend.ppc.vector_ext import VectorAssembler
class IntOpAssembler(object):
@@ -1322,12 +1323,12 @@
mc.b_abs(target)
mc.copy_to_raw_memory(oldadr)
-
class OpAssembler(IntOpAssembler, GuardOpAssembler,
MiscOpAssembler, FieldOpAssembler,
StrOpAssembler, CallOpAssembler,
UnicodeOpAssembler, ForceOpAssembler,
- AllocOpAssembler, FloatOpAssembler):
+ AllocOpAssembler, FloatOpAssembler,
+ VectorAssembler):
_mixin_ = True
def nop(self):
diff --git a/rpython/jit/backend/ppc/regalloc.py
b/rpython/jit/backend/ppc/regalloc.py
--- a/rpython/jit/backend/ppc/regalloc.py
+++ b/rpython/jit/backend/ppc/regalloc.py
@@ -27,6 +27,7 @@
from rpython.jit.codewriter.effectinfo import EffectInfo
from rpython.rlib import rgc
from rpython.rlib.rarithmetic import r_uint
+from rpython.jit.backend.ppc.vector_ext import VectorRegalloc
LIMIT_LOOP_BREAK = 15000 # should be much smaller than 32 KB
@@ -135,6 +136,17 @@
self.temp_boxes.append(box)
return reg
+class VectorRegisterManager(RegisterManager):
+ all_regs = r.MANAGED_VECTOR_REGS
+ box_types = [INT, FLOAT]
+ save_around_call_regs = [] # ??? lookup the ABI
+ assert set(save_around_call_regs).issubset(all_regs)
+
+ def __init__(self, longevity, frame_manager=None, assembler=None):
+ RegisterManager.__init__(self, longevity, frame_manager, assembler)
+
+ def ensure_reg(self, box):
+ raise NotImplementedError
class PPCFrameManager(FrameManager):
def __init__(self, base_ofs):
@@ -155,8 +167,7 @@
assert isinstance(loc, locations.StackLocation)
return loc.position
-
-class Regalloc(BaseRegalloc):
+class Regalloc(BaseRegalloc, VectorRegalloc):
def __init__(self, assembler=None):
self.cpu = assembler.cpu
@@ -180,6 +191,8 @@
assembler = self.assembler)
self.fprm = FPRegisterManager(self.longevity, frame_manager = self.fm,
assembler = self.assembler)
+ self.vrm = VectorRegisterManager(self.longevity, frame_manager =
self.fm,
+ assembler = self.assembler)
return operations
def prepare_loop(self, inputargs, operations, looptoken, allgcrefs):
@@ -287,6 +300,7 @@
self.assembler.mc.mark_op(op)
self.rm.position = i
self.fprm.position = i
+ self.vrm.position = i
opnum = op.opnum
if rop.has_no_side_effect(opnum) and op not in self.longevity:
i += 1
@@ -297,6 +311,8 @@
box = op.getarg(j)
if box.type != FLOAT:
self.rm.temp_boxes.append(box)
+ elif box.is_vector():
+ self.vrm.temp_boxes.append(box)
else:
self.fprm.temp_boxes.append(box)
#
@@ -309,6 +325,7 @@
self.possibly_free_var(op)
self.rm._check_invariants()
self.fprm._check_invariants()
+ self.vrm._check_invariants()
if self.assembler.mc.get_relative_pos() > self.limit_loop_break:
self.assembler.break_long_loop()
self.limit_loop_break = (self.assembler.mc.get_relative_pos() +
diff --git a/rpython/jit/backend/ppc/register.py
b/rpython/jit/backend/ppc/register.py
--- a/rpython/jit/backend/ppc/register.py
+++ b/rpython/jit/backend/ppc/register.py
@@ -51,6 +51,8 @@
MANAGED_FP_REGS = VOLATILES_FLOAT #+ NONVOLATILES_FLOAT
+MANAGED_VECTOR_REGS = ALL_VECTOR_REGS
+
assert RCS1 in MANAGED_REGS and RCS1 in NONVOLATILES
assert RCS2 in MANAGED_REGS and RCS2 in NONVOLATILES
assert RCS3 in MANAGED_REGS and RCS3 in NONVOLATILES
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -17,7 +17,7 @@
llop.debug_print(lltype.Void, msg)
raise NotImplementedError(msg)
-class PPCVectorAssemblerMixin(object):
+class VectorAssembler(object):
_mixin_ = True
#def genop_guard_vec_guard_true(self, guard_op, guard_token, locs, resloc):
@@ -510,30 +510,36 @@
#def genop_vec_cast_singlefloat_to_float(self, op, arglocs, resloc):
# self.mc.CVTPS2PD(resloc, arglocs[0])
-clas#s VectorRegallocMixin(object):
- #_mixin_ = True
+class VectorRegalloc(object):
+ _mixin_ = True
- #def _consider_vec_getarrayitem(self, op):
- # descr = op.getdescr()
- # assert isinstance(descr, ArrayDescr)
- # assert not descr.is_array_of_pointers() and \
- # not descr.is_array_of_structs()
- # itemsize, ofs, _ = unpack_arraydescr(descr)
- # integer = not (descr.is_array_of_floats() or descr.getconcrete_type()
== FLOAT)
- # aligned = False
- # args = op.getarglist()
- # base_loc = self.rm.make_sure_var_in_reg(op.getarg(0), args)
- # ofs_loc = self.rm.make_sure_var_in_reg(op.getarg(1), args)
- # result_loc = self.force_allocate_reg(op)
- # self.perform(op, [base_loc, ofs_loc, imm(itemsize), imm(ofs),
- # imm(integer), imm(aligned)], result_loc)
+ def force_allocate_vector_reg(self, op):
+ forbidden_vars = self.vrm.temp_boxes
+ self.vrm.force_allocate_reg(op, forbidden_vars)
- #consider_vec_getarrayitem_raw_i = _consider_vec_getarrayitem
- #consider_vec_getarrayitem_raw_f = _consider_vec_getarrayitem
- #consider_vec_getarrayitem_gc_i = _consider_vec_getarrayitem
- #consider_vec_getarrayitem_gc_f = _consider_vec_getarrayitem
- #consider_vec_raw_load_i = _consider_vec_getarrayitem
- #consider_vec_raw_load_f = _consider_vec_getarrayitem
+ def _consider_load(self, op):
+ descr = op.getdescr()
+ assert isinstance(descr, ArrayDescr)
+ assert not descr.is_array_of_pointers() and \
+ not descr.is_array_of_structs()
+ itemsize, ofs, _ = unpack_arraydescr(descr)
+ integer = not (descr.is_array_of_floats() or descr.getconcrete_type()
== FLOAT)
+ aligned = False
+ args = op.getarglist()
+ a0 = op.getarg(0)
+ a1 = op.getarg(1)
+ base_loc = self.ensure_reg(a0)
+ ofs_loc = self.ensure_reg(a1)
+ result_loc = self.force_allocate_vector_reg(op)
+ self.perform(op, [base_loc, ofs_loc, imm(itemsize), imm(ofs),
+ imm(integer), imm(aligned)], result_loc)
+
+ consider_vec_getarrayitem_raw_i = _consider_load
+ consider_vec_getarrayitem_raw_f = _consider_load
+ consider_vec_getarrayitem_gc_i = _consider_load
+ consider_vec_getarrayitem_gc_f = _consider_load
+ consider_vec_raw_load_i = _consider_load
+ consider_vec_raw_load_f = _consider_load
#def _consider_vec_setarrayitem(self, op):
# descr = op.getdescr()
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