Author: Richard Plangger <planri...@gmail.com>
Branch: ppc-vsx-support
Changeset: r85311:771785582074
Date: 2016-06-21 17:09 +0200
http://bitbucket.org/pypy/pypy/changeset/771785582074/
Log: (ppc) implemented vec_int_add
diff --git a/rpython/jit/backend/ppc/codebuilder.py
b/rpython/jit/backend/ppc/codebuilder.py
--- a/rpython/jit/backend/ppc/codebuilder.py
+++ b/rpython/jit/backend/ppc/codebuilder.py
@@ -620,6 +620,9 @@
# arith & logic
vaddudm = VX(4, XO8=192)
+ vadduwm = VX(4, XO8=128)
+ vadduhm = VX(4, XO8=64)
+ vaddubm = VX(4, XO8=0)
# shift, perm and select
lvsl = XV(31, XO1=6)
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -123,11 +123,11 @@
resloc, loc0, loc1, size_loc = arglocs
size = size_loc.value
if size == 1:
- raise NotImplementedError
+ self.mc.vaddubm(resloc.value, loc0.value, loc1.value)
elif size == 2:
- raise NotImplementedError
+ self.mc.vadduhm(resloc.value, loc0.value, loc1.value)
elif size == 4:
- raise NotImplementedError
+ self.mc.vadduwm(resloc.value, loc0.value, loc1.value)
elif size == 8:
self.mc.vaddudm(resloc.value, loc0.value, loc1.value)
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