Author: Richard Plangger <[email protected]>
Branch: ppc-vsx-support
Changeset: r85312:03a28e77e69d
Date: 2016-06-21 17:24 +0200
http://bitbucket.org/pypy/pypy/changeset/03a28e77e69d/
Log: (ppc) implemented vec_int_sub
diff --git a/rpython/jit/backend/ppc/codebuilder.py
b/rpython/jit/backend/ppc/codebuilder.py
--- a/rpython/jit/backend/ppc/codebuilder.py
+++ b/rpython/jit/backend/ppc/codebuilder.py
@@ -624,6 +624,13 @@
vadduhm = VX(4, XO8=64)
vaddubm = VX(4, XO8=0)
+ vsubudm = VX(4, XO8=1216)
+ vsubuwm = VX(4, XO8=1152)
+ vsubuhm = VX(4, XO8=1088)
+ vsububm = VX(4, XO8=1024)
+
+
+
# shift, perm and select
lvsl = XV(31, XO1=6)
lvsr = XV(31, XO1=38)
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -131,6 +131,21 @@
elif size == 8:
self.mc.vaddudm(resloc.value, loc0.value, loc1.value)
+ def emit_vec_int_sub(self, op, arglocs, regalloc):
+ resloc, loc0, loc1, size_loc = arglocs
+ size = size_loc.value
+ if size == 1:
+ # TODO verify if unsigned subtract is the wanted feature
+ self.mc.vsububm(resloc.value, loc0.value, loc1.value)
+ elif size == 2:
+ # TODO verify if unsigned subtract is the wanted feature
+ self.mc.vsubuhm(resloc.value, loc0.value, loc1.value)
+ elif size == 4:
+ # TODO verify if unsigned subtract is the wanted feature
+ self.mc.vsubuwm(resloc.value, loc0.value, loc1.value)
+ elif size == 8:
+ self.mc.vsubudm(resloc.value, loc0.value, loc1.value)
+
def emit_vec_float_add(self, op, arglocs, resloc):
resloc, loc0, loc1, itemsize_loc = arglocs
itemsize = itemsize_loc.value
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