Author: Richard Plangger <[email protected]>
Branch: ppc-vsx-support
Changeset: r85360:0ad6556517cf
Date: 2016-06-22 18:10 +0200
http://bitbucket.org/pypy/pypy/changeset/0ad6556517cf/
Log: (ppc) added impl for float_abs & float_neg.
diff --git a/rpython/jit/backend/ppc/codebuilder.py
b/rpython/jit/backend/ppc/codebuilder.py
--- a/rpython/jit/backend/ppc/codebuilder.py
+++ b/rpython/jit/backend/ppc/codebuilder.py
@@ -62,6 +62,7 @@
XFX = Form("CRM", "rS", "XO1")
XLL = Form("LL", "XO1")
XX1 = Form("fvrT", "rA", "rB", "XO1")
+XX2 = Form("fvrT", "fvrB", "XO5")
XX3 = Form("fvrT", "fvrA", "fvrB", "XO9")
XV = Form("ivrT", "rA", "rB", "XO1")
VX = Form("ivrT", "ivrA", "ivrB", "XO8")
@@ -611,6 +612,14 @@
xvdivdp = XX3(60, XO9=102)
xvdivsp = XX3(60, XO9=88)
+ # neg
+ xvnegdp = XX2(60, XO5=505)
+ xvabssp = XX2(60, XO5=441)
+
+ # abs
+ xvabsdp = XX2(60, XO5=473)
+ xvabssp = XX2(60, XO5=409)
+
# INTEGER
# -------
@@ -644,8 +653,6 @@
# vector move register is alias to vector or
vmr = vor
-
-
# shift, perm and select
lvsl = XV(31, XO1=6)
lvsr = XV(31, XO1=38)
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -213,6 +213,26 @@
# TODO
self.regalloc_mov(loc0, resloc)
+ def emit_vec_float_abs(self, op, arglocs, resloc):
+ resloc, argloc, sizeloc = arglocs
+ size = sizeloc.value
+ if size == 4:
+ self.mc.xvabssp(resloc.value, argloc.value)
+ elif size == 8:
+ self.mc.xvabsdp(resloc.value, argloc.value)
+ else:
+ notimplemented("[ppc/assembler] float abs for size %d" % size)
+
+ def emit_vec_float_neg(self, op, arglocs, resloc):
+ resloc, argloc, sizeloc = arglocs
+ size = sizeloc.value
+ if size == 4:
+ self.mc.xvnegsp(resloc.value, argloc.value)
+ elif size == 8:
+ self.mc.xvnegdp(resloc.value, argloc.value)
+ else:
+ notimplemented("[ppc/assembler] float neg for size %d" % size)
+
#def genop_guard_vec_guard_true(self, guard_op, guard_token, locs, resloc):
# self.implement_guard(guard_token)
@@ -328,22 +348,6 @@
# # entries before) become ones
# self.mc.PCMPEQ(loc, temp, sizeloc.value)
- #def genop_vec_float_abs(self, op, arglocs, resloc):
- # src, sizeloc = arglocs
- # size = sizeloc.value
- # if size == 4:
- # self.mc.ANDPS(src, heap(self.single_float_const_abs_addr))
- # elif size == 8:
- # self.mc.ANDPD(src, heap(self.float_const_abs_addr))
-
- #def genop_vec_float_neg(self, op, arglocs, resloc):
- # src, sizeloc = arglocs
- # size = sizeloc.value
- # if size == 4:
- # self.mc.XORPS(src, heap(self.single_float_const_neg_addr))
- # elif size == 8:
- # self.mc.XORPD(src, heap(self.float_const_neg_addr))
-
#def genop_vec_float_eq(self, op, arglocs, resloc):
# _, rhsloc, sizeloc = arglocs
# size = sizeloc.value
@@ -659,17 +663,16 @@
- #def prepare_vec_arith_unary(self, op):
- # lhs = op.getarg(0)
- # assert isinstance(lhs, VectorOp)
- # args = op.getarglist()
- # res = self.xrm.force_result_in_reg(op, op.getarg(0), args)
- # self.perform(op, [res, imm(lhs.bytesize)], res)
+ def prepare_vec_arith_unary(self, op):
+ a0 = op.getarg(0)
+ loc0 = self.ensure_vector_reg(a0)
+ resloc = self.force_allocate_vector_reg(op)
+ sizeloc = imm(op.bytesize)
+ return [resloc, loc0, sizeloc]
- #prepare_vec_float_neg = prepare_vec_arith_unary
- #prepare_vec_float_abs = prepare_vec_arith_unary
- #del prepare_vec_arith_unary
-
+ prepare_vec_float_neg = prepare_vec_arith_unary
+ prepare_vec_float_abs = prepare_vec_arith_unary
+ del prepare_vec_arith_unary
#def prepare_vec_float_eq(self, op):
# assert isinstance(op, VectorOp)
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