Author: Richard Plangger <[email protected]>
Branch: ppc-vsx-support
Changeset: r85562:c97b2b5608a4
Date: 2016-07-05 16:27 +0200
http://bitbucket.org/pypy/pypy/changeset/c97b2b5608a4/
Log: remove the integer register allocator. float and int vector register
are colocated (i.e. float 32 -> int 0, float 33 -> int 1, ...), this
makes things much easier
diff --git a/rpython/jit/backend/ppc/regalloc.py
b/rpython/jit/backend/ppc/regalloc.py
--- a/rpython/jit/backend/ppc/regalloc.py
+++ b/rpython/jit/backend/ppc/regalloc.py
@@ -142,9 +142,9 @@
self.temp_boxes.append(box)
return reg
-class IntegerVectorRegisterManager(RegisterManager):
- all_regs = r.MANAGED_INTEGER_VECTOR_REGS
- box_types = [INT]
+class VectorRegisterManager(RegisterManager):
+ all_regs = r.MANAGED_FLOAT_VECTOR_REGS
+ box_types = [FLOAT, INT]
save_around_call_regs = [] # ??? lookup the ABI
assert set(save_around_call_regs).issubset(all_regs)
@@ -154,26 +154,11 @@
def ensure_reg(self, box):
raise NotImplementedError
- def get_scratch_reg(self):
- box = TempInt()
- reg = self.force_allocate_reg(box, forbidden_vars=self.temp_boxes)
- self.temp_boxes.append(box)
- return reg
-
-class FloatVectorRegisterManager(IntegerVectorRegisterManager):
- all_regs = r.MANAGED_FLOAT_VECTOR_REGS
- box_types = [FLOAT]
- save_around_call_regs = [] # ??? lookup the ABI
- assert set(save_around_call_regs).issubset(all_regs)
-
- def __init__(self, longevity, frame_manager=None, assembler=None):
- RegisterManager.__init__(self, longevity, frame_manager, assembler)
-
- def ensure_reg(self, box):
- raise NotImplementedError
-
- def get_scratch_reg(self):
- box = TempFloat()
+ def get_scratch_reg(self, type=INT):
+ if type == FLOAT:
+ box = TempFloat()
+ else:
+ box = TempInt()
reg = self.force_allocate_reg(box, forbidden_vars=self.temp_boxes)
self.temp_boxes.append(box)
return reg
@@ -221,10 +206,8 @@
assembler = self.assembler)
self.fprm = FPRegisterManager(self.longevity, frame_manager = self.fm,
assembler = self.assembler)
- self.vrm = FloatVectorRegisterManager(self.longevity, frame_manager =
self.fm,
- assembler = self.assembler)
- self.ivrm = IntegerVectorRegisterManager(self.longevity, frame_manager
= self.fm,
- assembler = self.assembler)
+ self.vrm = VectorRegisterManager(self.longevity, frame_manager =
self.fm,
+ assembler = self.assembler)
return operations
def prepare_loop(self, inputargs, operations, looptoken, allgcrefs):
@@ -286,16 +269,13 @@
def possibly_free_var(self, var):
if var is not None:
- if var.type == FLOAT:
- if var.is_vector():
+ if var.is_vector():
+ if var.type != VOID:
self.vrm.possibly_free_var(var)
- else:
- self.fprm.possibly_free_var(var)
+ elif var.type == FLOAT:
+ self.fprm.possibly_free_var(var)
elif var.type == INT:
- if var.is_vector():
- self.ivrm.possibly_free_var(var)
- else:
- self.rm.possibly_free_var(var)
+ self.rm.possibly_free_var(var)
def possibly_free_vars(self, vars):
for var in vars:
@@ -339,7 +319,6 @@
self.rm.position = i
self.fprm.position = i
self.vrm.position = i
- self.ivrm.position = i
opnum = op.opnum
if rop.has_no_side_effect(opnum) and op not in self.longevity:
i += 1
@@ -348,16 +327,13 @@
#
for j in range(op.numargs()):
box = op.getarg(j)
- if box.type != FLOAT:
- if box.is_vector():
- self.ivrm.temp_boxes.append(box)
- else:
- self.rm.temp_boxes.append(box)
+ if box.is_vector():
+ if box.type != VOID:
+ self.vrm.temp_boxes.append(box)
+ elif box.type != FLOAT:
+ self.rm.temp_boxes.append(box)
else:
- if box.is_vector():
- self.vrm.temp_boxes.append(box)
- else:
- self.fprm.temp_boxes.append(box)
+ self.fprm.temp_boxes.append(box)
#
if not we_are_translated() and opnum == rop.FORCE_SPILL:
self._consider_force_spill(op)
@@ -369,7 +345,6 @@
self.rm._check_invariants()
self.fprm._check_invariants()
self.vrm._check_invariants()
- self.ivrm._check_invariants()
if self.assembler.mc.get_relative_pos() > self.limit_loop_break:
self.assembler.break_long_loop(self)
self.limit_loop_break = (self.assembler.mc.get_relative_pos() +
@@ -413,10 +388,7 @@
def loc(self, var):
if var.is_vector():
- if var.type == FLOAT:
- return self.vrm.loc(var)
- else:
- return self.ivrm.loc(var)
+ return self.vrm.loc(var)
else:
if var.type == FLOAT:
return self.fprm.loc(var)
@@ -487,7 +459,6 @@
self.rm.free_temp_vars()
self.fprm.free_temp_vars()
self.vrm.free_temp_vars()
- self.ivrm.free_temp_vars()
# ******************************************************
# * P R E P A R E O P E R A T I O N S *
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -51,8 +51,8 @@
else:
resval = result_loc.value
# either doubleword integer 1 (2x) or word integer 1 (4x)
- ones = regalloc.ivrm.get_scratch_reg().value
- zeros = regalloc.ivrm.get_scratch_reg().value
+ ones = regalloc.vrm.get_scratch_reg(type=INT).value
+ zeros = regalloc.vrm.get_scratch_reg(type=INT).value
asm.mc.vxor(zeros, zeros, zeros)
if size == 4:
asm.mc.vspltisw(ones, 1)
@@ -121,15 +121,15 @@
indexloc = self._apply_offset(indexloc, baseofs)
assert baseofs.value == 0
if integer_loc.value:
- Vloloc = regalloc.ivrm.get_scratch_reg()
- Vhiloc = regalloc.ivrm.get_scratch_reg()
- Vploc = regalloc.ivrm.get_scratch_reg()
+ Vloloc = regalloc.vrm.get_scratch_reg(type=INT)
+ Vhiloc = regalloc.vrm.get_scratch_reg(type=INT)
+ Vploc = regalloc.vrm.get_scratch_reg(type=INT)
tloc = regalloc.rm.get_scratch_reg()
- V1sloc = regalloc.ivrm.get_scratch_reg()
+ V1sloc = regalloc.vrm.get_scratch_reg(type=INT)
V1s = V1sloc.value
- V0sloc = regalloc.ivrm.get_scratch_reg()
+ V0sloc = regalloc.vrm.get_scratch_reg(type=INT)
V0s = V0sloc.value
- Vmaskloc = regalloc.ivrm.get_scratch_reg()
+ Vmaskloc = regalloc.vrm.get_scratch_reg(type=INT)
Vmask = Vmaskloc.value
Vlo = Vhiloc.value
Vhi = Vloloc.value
@@ -372,7 +372,7 @@
def emit_vec_int_is_true(self, op, arglocs, regalloc):
resloc, argloc, sizeloc = arglocs
size = sizeloc.value
- tmp = regalloc.ivrm.get_scratch_reg().value
+ tmp = regalloc.vrm.get_scratch_reg(type=INT).value
self.mc.vxor(tmp, tmp, tmp)
# argloc[i] > 0:
# For an unsigned integer that is equivalent to argloc[i] != 0
@@ -616,13 +616,11 @@
def emit_vec_cast_float_to_int(self, op, arglocs, regalloc):
res, l0 = arglocs
offloc = regalloc.rm.get_scratch_reg()
- v0 = regalloc.vrm.get_scratch_reg()
+ v0 = regalloc.vrm.get_scratch_reg(type=INT)
off = offloc.value
# SP is always 16 byte aligned, and PARAM_SAVE_AREA_OFFSET % 16 == 0
self.mc.load_imm(offloc, PARAM_SAVE_AREA_OFFSET)
- self.mc.xvcvdpsxds(v0.value, l0.value)
- self.mc.stxvd2x(v0.value, off, r.SP.value)
- self.mc.lvx(res.value, off, r.SP.value)
+ self.mc.xvcvdpsxds(res.value, l0.value)
# needed as soon as PPC's support_singlefloat is implemented!
#def genop_vec_cast_singlefloat_to_float(self, op, arglocs, regalloc):
@@ -637,10 +635,7 @@
def force_allocate_vector_reg(self, op):
forbidden_vars = self.vrm.temp_boxes
- if op.type == FLOAT:
- return self.vrm.force_allocate_reg(op, forbidden_vars)
- else:
- return self.ivrm.force_allocate_reg(op, forbidden_vars)
+ return self.vrm.force_allocate_reg(op, forbidden_vars)
def force_allocate_vector_reg_or_cc(self, op):
assert op.type == INT
@@ -654,12 +649,8 @@
return self.force_allocate_vector_reg(op)
def ensure_vector_reg(self, box):
- if box.type == FLOAT:
- return self.vrm.make_sure_var_in_reg(box,
- forbidden_vars=self.vrm.temp_boxes)
- else:
- return self.ivrm.make_sure_var_in_reg(box,
- forbidden_vars=self.ivrm.temp_boxes)
+ return self.vrm.make_sure_var_in_reg(box,
+ forbidden_vars=self.vrm.temp_boxes)
def _prepare_load(self, op):
descr = op.getdescr()
@@ -691,9 +682,9 @@
ofs_loc = self.ensure_reg(a1)
result_loc = self.force_allocate_vector_reg(op)
tloc = self.rm.get_scratch_reg()
- Vhiloc = self.ivrm.get_scratch_reg()
- Vloloc = self.ivrm.get_scratch_reg()
- Vploc = self.ivrm.get_scratch_reg()
+ Vhiloc = self.vrm.get_scratch_reg(type=INT)
+ Vloloc = self.vrm.get_scratch_reg(type=INT)
+ Vploc = self.vrm.get_scratch_reg(type=INT)
return [result_loc, base_loc, ofs_loc, imm(itemsize), imm(ofs),
Vhiloc, Vloloc, Vploc, tloc]
diff --git a/rpython/jit/metainterp/test/test_vector.py
b/rpython/jit/metainterp/test/test_vector.py
--- a/rpython/jit/metainterp/test/test_vector.py
+++ b/rpython/jit/metainterp/test/test_vector.py
@@ -613,7 +613,7 @@
yield (size, Typ(*t1), Typ(*t2), Typ(*t3), op[0], op[1])
types = [('rffi.DOUBLE', 'float', 'float'),
('rffi.SIGNED', 'int', 'int'),
- ('rffi.FLOAT', 'rffi.r_singlefloat', 'float'),
+ #('rffi.FLOAT', 'rffi.r_singlefloat', 'float'),
]
operators = [('add', '+'),
]
@@ -629,11 +629,11 @@
vector_b = lltype.malloc(T2, size, flavor='raw')
vector_c = lltype.malloc(T3, size, flavor='raw')
for i in range(size):
- vector_a[i] = {type_a_storecast}(i+1)
+ vector_a[i] = {type_a_storecast}(1)
for i in range(size):
- vector_b[i] = {type_b_storecast}(i+1)
+ vector_b[i] = {type_b_storecast}(1)
for i in range(size):
- vector_c[i] = {type_c_storecast}(i+1)
+ vector_c[i] = {type_c_storecast}(1)
i = 0
while i < size:
myjitdriver.jit_merge_point()
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