Author: Richard Plangger <planri...@gmail.com>
Branch: ppc-vsx-support
Changeset: r85971:a88c5ddefcb0
Date: 2016-08-01 21:22 +0200
http://bitbucket.org/pypy/pypy/changeset/a88c5ddefcb0/
Log: added three more tests to ensure enforce_var_in_vector_reg works
(found one issue)
diff --git a/rpython/jit/backend/x86/test/test_x86vector.py
b/rpython/jit/backend/x86/test/test_x86vector.py
--- a/rpython/jit/backend/x86/test/test_x86vector.py
+++ b/rpython/jit/backend/x86/test/test_x86vector.py
@@ -1,10 +1,14 @@
import py
from rpython.jit.backend.x86.regloc import *
+from rpython.jit.backend.x86.regalloc import (RegAlloc,
+ X86FrameManager, X86XMMRegisterManager, X86RegisterManager)
+from rpython.jit.backend.x86.vector_ext import TempVector
from rpython.jit.backend.x86.test import test_basic
from rpython.jit.backend.x86.test.test_assembler import \
(TestRegallocPushPop as BaseTestAssembler)
from rpython.jit.metainterp.test import test_vector
from rpython.rtyper.lltypesystem import lltype
+from rpython.jit.backend.detect_cpu import getcpuclass
class TestBasic(test_basic.Jit386Mixin, test_vector.VectorizeTests):
# for the individual tests see
@@ -26,6 +30,30 @@
enable_opts =
'intbounds:rewrite:virtualize:string:earlyforce:pure:heap:unroll'
+@py.test.fixture
+def regalloc(request):
+ from rpython.jit.backend.x86.regalloc import X86FrameManager
+ from rpython.jit.backend.x86.regalloc import X86XMMRegisterManager
+ class FakeToken:
+ class compiled_loop_token:
+ asmmemmgr_blocks = None
+ cpu = getcpuclass()(None, None)
+ cpu.setup()
+ if cpu.HAS_CODEMAP:
+ cpu.codemap.setup()
+ looptoken = FakeToken()
+ asm = cpu.assembler
+ asm.setup_once()
+ asm.setup(looptoken)
+ regalloc = RegAlloc(asm)
+ regalloc.fm = fm = X86FrameManager(cpu.get_baseofs_of_frame_field())
+ regalloc.rm = X86RegisterManager({}, frame_manager = fm, assembler = asm)
+ regalloc.xrm = X86XMMRegisterManager({}, frame_manager = fm, assembler =
asm)
+ request.cls.asm = asm
+ request.cls.regalloc = regalloc
+
+
+
class TestAssembler(BaseTestAssembler):
def imm_4_int32(self, a, b, c, d):
@@ -88,3 +116,48 @@
res = self.do_test(callback) & 0xffffffff
assert res == 22
+ def test_enforce_var(self, regalloc):
+ arg = TempVector('f')
+ args = []
+ self.regalloc.fm.bindings[arg] = FrameLoc(0, 64, 'f')
+ reg = self.regalloc.enforce_var_in_vector_reg(arg, args, xmm0)
+ assert reg is xmm0
+
+ def test_enforce_var_xmm0_forbidden(self, regalloc):
+ arg = TempVector('f')
+ arg1 = TempVector('f')
+ args = [arg1]
+ xrm = self.regalloc.xrm
+ xrm.reg_bindings[arg1] = xmm0
+ fr = xrm.free_regs
+ xrm.free_regs = [r for r in fr if r is not xmm0]
+ self.regalloc.fm.bindings[arg] = FrameLoc(0, 64, 'f')
+ reg = self.regalloc.enforce_var_in_vector_reg(arg, args, xmm0)
+ assert reg is xmm0
+ assert len(xrm.reg_bindings) == 2
+ assert xrm.reg_bindings[arg] == xmm0
+ assert xrm.reg_bindings[arg1] != xmm0
+
+ def test_enforce_var_spill(self, regalloc):
+ arg = TempVector('f')
+ arg1 = TempVector('f')
+ arg2 = TempVector('f')
+ args = []
+ xrm = self.regalloc.xrm
+ xrm.reg_bindings[arg1] = xmm0
+ xrm.reg_bindings[arg2] = xmm1
+ xrm.longevity[arg1] = (0,1)
+ xrm.longevity[arg2] = (0,2)
+ xrm.longevity[arg] = (0,3)
+ fr = xrm.free_regs
+ xrm.free_regs = []
+ self.regalloc.fm.bindings[arg] = FrameLoc(0, 64, 'f')
+ self.regalloc.fm.bindings[arg2] = FrameLoc(0, 72, 'f')
+ reg = self.regalloc.enforce_var_in_vector_reg(arg, args, xmm0)
+ assert reg is xmm0
+ assert len(xrm.reg_bindings) == 2
+ assert xrm.reg_bindings[arg] == xmm0
+ assert xrm.reg_bindings[arg1] == xmm1
+ assert arg2 not in xrm.reg_bindings
+
+
diff --git a/rpython/jit/backend/x86/vector_ext.py
b/rpython/jit/backend/x86/vector_ext.py
--- a/rpython/jit/backend/x86/vector_ext.py
+++ b/rpython/jit/backend/x86/vector_ext.py
@@ -10,7 +10,7 @@
xmm5, xmm6, xmm7, xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14,
X86_64_SCRATCH_REG, X86_64_XMM_SCRATCH_REG, AddressLoc)
from rpython.jit.backend.llsupport.vector_ext import VectorExt
-from rpython.jit.backend.llsupport.regalloc import get_scale, TempVar
+from rpython.jit.backend.llsupport.regalloc import get_scale, TempVar,
NoVariableToSpill
from rpython.jit.metainterp.resoperation import (rop, ResOperation,
VectorOp, VectorGuardOp)
from rpython.rlib.objectmodel import we_are_translated, always_inline
@@ -317,7 +317,7 @@
# register, and we emit a load from the cc into this register.
if resloc is ebp:
- self.assembler.guard_success_cc = condition
+ self.guard_success_cc = rev_cond
else:
assert lhsloc is xmm0
maskloc = X86_64_XMM_SCRATCH_REG
@@ -654,7 +654,11 @@
# do we have a free register?
if len(xrm.free_regs) == 0:
# spill a non forbidden variable
- self._spill_var(candidate_to_spill, forbidden_vars, None)
+ if not candidate_to_spill:
+ raise NoVariableToSpill
+ reg = xrm.reg_bindings[candidate_to_spill]
+ xrm._spill_var(candidate_to_spill, forbidden_vars, None)
+ xrm.free_regs.append(reg)
loc = xrm.free_regs.pop()
self.assembler.mov(selected_reg, loc)
reg = xrm.reg_bindings.get(arg, None)
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