Author: Richard Plangger <planri...@gmail.com>
Branch: zarch-simd-support
Changeset: r87070:13d4d6bd1c2f
Date: 2016-09-13 11:56 +0200
http://bitbucket.org/pypy/pypy/changeset/13d4d6bd1c2f/
Log: add runtime check to detect vector facility
diff --git a/rpython/jit/backend/ppc/vector_ext.py
b/rpython/jit/backend/ppc/vector_ext.py
--- a/rpython/jit/backend/ppc/vector_ext.py
+++ b/rpython/jit/backend/ppc/vector_ext.py
@@ -20,7 +20,7 @@
from rpython.jit.backend.llsupport.asmmemmgr import MachineDataBlockWrapper
from rpython.rtyper.lltypesystem import lltype, rffi
from rpython.jit.codewriter import longlong
-from rpython.jit.backend.ppc.detect_feature import detect_vsx
+from rpython.jit.backend.zarch.detect_feature import detect_simd_z
from rpython.rlib.objectmodel import always_inline
def not_implemented(msg):
@@ -85,7 +85,7 @@
class AltiVectorExt(VectorExt):
def setup_once(self, asm):
- if detect_vsx():
+ if detect_simd_z():
self.enable(16, accum=True)
asm.setup_once_vector()
self._setup = True
diff --git a/rpython/jit/backend/zarch/runner.py
b/rpython/jit/backend/zarch/runner.py
--- a/rpython/jit/backend/zarch/runner.py
+++ b/rpython/jit/backend/zarch/runner.py
@@ -16,6 +16,8 @@
supports_floats = True
from rpython.jit.backend.zarch.registers import JITFRAME_FIXED_SIZE
+ vector_ext = SIMDZVectorExt()
+
backend_name = 'zarch'
IS_64_BIT = True
diff --git a/rpython/jit/backend/zarch/vector_ext.py
b/rpython/jit/backend/zarch/vector_ext.py
--- a/rpython/jit/backend/zarch/vector_ext.py
+++ b/rpython/jit/backend/zarch/vector_ext.py
@@ -182,10 +182,6 @@
elif itemsize == 8:
self.mc.xvdivdp(resloc.value, loc0.value, loc1.value)
- def emit_vec_int_mul(self, op, arglocs, regalloc):
- raise NotImplementedError
- pass # TODO
-
def emit_vec_int_and(self, op, arglocs, regalloc):
resloc, loc0, loc1, sizeloc = arglocs
self.mc.vand(resloc.value, loc0.value, loc1.value)
diff --git a/rpython/rlib/jit.py b/rpython/rlib/jit.py
--- a/rpython/rlib/jit.py
+++ b/rpython/rlib/jit.py
@@ -553,7 +553,7 @@
'optimizations to enable, or all = %s' % ENABLE_ALL_OPTS,
'max_unroll_recursion': 'how many levels deep to unroll a recursive
function',
'vec': 'turn on the vectorization optimization (vecopt). ' \
- 'Supports powerpc (SVX), x86 (SSE 4.1)',
+ 'Supports x86 (SSE 4.1), powerpc (SVX), s390x',
'vec_all': 'try to vectorize trace loops that occur outside of the numpy
library.',
'vec_cost': 'threshold for which traces to bail. 0 means the costs.',
'vec_length': 'the amount of instructions allowed in "all" traces.',
diff --git a/rpython/translator/platform/arch/s390x.py
b/rpython/translator/platform/arch/s390x.py
--- a/rpython/translator/platform/arch/s390x.py
+++ b/rpython/translator/platform/arch/s390x.py
@@ -1,7 +1,6 @@
import re
def extract_s390x_cpu_ids(lines):
- """ NOT_RPYTHON """
ids = []
re_number = re.compile("processor (\d+):")
@@ -41,7 +40,6 @@
def s390x_cpu_revision():
- """ NOT_RPYTHON """
# linux kernel does the same classification
#
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20131028/193311.html
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