Author: Richard Plangger <[email protected]>
Branch: ppc-vsx-support
Changeset: r87225:0cc906e34289
Date: 2016-09-19 14:29 +0200
http://bitbucket.org/pypy/pypy/changeset/0cc906e34289/
Log: translation issues
diff --git a/rpython/jit/backend/zarch/assembler.py
b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -896,7 +896,7 @@
ofs = self.cpu.get_ofs_of_frame_field('jf_gcmap')
mc.LG(r.SCRATCH, l.addr(ofs, r.SPP))
- def break_long_loop(self):
+ def break_long_loop(self, regalloc):
# If the loop is too long, the guards in it will jump forward
# more than 32 KB. We use an approximate hack to know if we
# should break the loop here with an unconditional "b" that
@@ -904,7 +904,7 @@
jmp_pos = self.mc.currpos()
self.mc.reserve_cond_jump()
- self.write_pending_failure_recoveries()
+ self.write_pending_failure_recoveries(regalloc)
currpos = self.mc.currpos()
pmc = OverwritingBuilder(self.mc, jmp_pos, 1)
diff --git a/rpython/jit/backend/zarch/instruction_builder.py
b/rpython/jit/backend/zarch/instruction_builder.py
--- a/rpython/jit/backend/zarch/instruction_builder.py
+++ b/rpython/jit/backend/zarch/instruction_builder.py
@@ -628,7 +628,7 @@
return 0
elif argtype == 'r' or argtype == 'r/m' or \
argtype == 'f' or argtype == 'eo' or \
- argtype == 'v':
+ argtype == 'v' or argtype == 'm':
return arg.value
elif argtype.startswith('i') or argtype.startswith('u') or
argtype.startswith('h'):
return arg.value
diff --git a/rpython/jit/backend/zarch/locations.py
b/rpython/jit/backend/zarch/locations.py
--- a/rpython/jit/backend/zarch/locations.py
+++ b/rpython/jit/backend/zarch/locations.py
@@ -247,6 +247,7 @@
from rpython.jit.backend.zarch.registers import JITFRAME_FIXED_SIZE
return base_ofs + WORD * (position + JITFRAME_FIXED_SIZE)
+imm3 = imm(1)
imm1 = imm(1)
imm0 = imm(0)
@@ -254,16 +255,17 @@
MASK_VEC_HWORD = 1
MASK_VEC_WORD = 2
MASK_VEC_DWORD = 3
+MASK_VEC_QWORD = 4
def itemsize_to_mask(v):
if v == 16:
- return MASK_VEC_QWORD
+ return imm(MASK_VEC_QWORD)
elif v == 8:
- return MASK_VEC_DWORD
+ return imm(MASK_VEC_DWORD)
elif v == 4:
- return MASK_VEC_WORD
+ return imm(MASK_VEC_WORD)
elif v == 2:
- return MASK_VEC_HWORD
+ return imm(MASK_VEC_HWORD)
elif v == 1:
- return MASK_VEC_BYTE
+ return imm(MASK_VEC_BYTE)
assert 0, "not supported itemsize to mask!"
diff --git a/rpython/jit/backend/zarch/regalloc.py
b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -615,7 +615,7 @@
self.fprm._check_invariants()
self.vrm._check_invariants()
if self.assembler.mc.get_relative_pos() > self.limit_loop_break:
- self.assembler.break_long_loop()
+ self.assembler.break_long_loop(self)
self.limit_loop_break = (self.assembler.mc.get_relative_pos() +
LIMIT_LOOP_BREAK)
i += 1
diff --git a/rpython/jit/backend/zarch/vector_ext.py
b/rpython/jit/backend/zarch/vector_ext.py
--- a/rpython/jit/backend/zarch/vector_ext.py
+++ b/rpython/jit/backend/zarch/vector_ext.py
@@ -21,6 +21,7 @@
from rpython.rtyper.lltypesystem import lltype, rffi
from rpython.jit.codewriter import longlong
from rpython.rlib.objectmodel import always_inline
+from rpython.jit.backend.zarch.arch import WORD
def not_implemented(msg):
msg = '[zarch/vector_ext] %s\n' % msg
@@ -30,7 +31,7 @@
@always_inline
def permi(v1,v2):
- return (v1 << 2 | v2) & 0xf
+ return l.imm((v1 << 2 | v2) & 0xf)
def flush_vec_cc(asm, regalloc, condition, size, resultloc):
# After emitting an instruction that leaves a boolean result in
@@ -91,7 +92,7 @@
resloc, loc0, loc1, itemsize_loc = arglocs
itemsize = itemsize_loc.value
if itemsize == 8:
- self.mc.VFA(resloc, loc0, loc1, 3, 0, 0)
+ self.mc.VFA(resloc, loc0, loc1, l.imm(3), l.imm(0), l.imm(0))
return
not_implemented("vec_float_add of size %d" % itemsize)
@@ -99,7 +100,7 @@
resloc, loc0, loc1, itemsize_loc = arglocs
itemsize = itemsize_loc.value
if itemsize == 8:
- self.mc.VFS(resloc, loc0, loc1, 3, 0, 0)
+ self.mc.VFS(resloc, loc0, loc1, l.imm(3), l.imm(0), l.imm(0))
return
not_implemented("vec_float_sub of size %d" % itemsize)
@@ -107,7 +108,7 @@
resloc, loc0, loc1, itemsize_loc = arglocs
itemsize = itemsize_loc.value
if itemsize == 8:
- self.mc.VFM(resloc, loc0, loc1, 3, 0, 0)
+ self.mc.VFM(resloc, loc0, loc1, l.imm(3), l.imm(0), l.imm(0))
return
not_implemented("vec_float_mul of size %d" % itemsize)
@@ -115,7 +116,7 @@
resloc, loc0, loc1, itemsize_loc = arglocs
itemsize = itemsize_loc.value
if itemsize == 8:
- self.mc.VFD(resloc, loc0, loc1, 3, 0, 0)
+ self.mc.VFD(resloc, loc0, loc1, l.imm(3), l.imm(0), l.imm(0))
return
not_implemented("vec_float_truediv of size %d" % itemsize)
@@ -141,17 +142,17 @@
resloc, argloc, sizeloc = arglocs
size = sizeloc.value
if size == 8:
- self.mc.VFPSO(resloc, argloc, 3, 0, 2)
+ self.mc.VFPSO(resloc, argloc, l.imm(3), l.imm(0), l.imm(2))
return
- not_implemented("vec_float_abs of size %d" % itemsize)
+ not_implemented("vec_float_abs of size %d" % size)
def emit_vec_float_neg(self, op, arglocs, regalloc):
resloc, argloc, sizeloc = arglocs
size = sizeloc.value
if size == 8:
- self.mc.VFPSO(resloc, argloc, 3, 0, 0)
+ self.mc.VFPSO(resloc, argloc, l.imm(3), l.imm(0), l.imm(0))
return
- not_implemented("vec_float_abs of size %d" % itemsize)
+ not_implemented("vec_float_abs of size %d" % size)
def emit_vec_guard_true(self, guard_op, arglocs, regalloc):
self._emit_guard(guard_op, arglocs)
@@ -189,7 +190,7 @@
size = sizeloc.value
tmploc = regalloc.vrm.get_scratch_reg()
self.mc.VX(tmploc, tmploc, tmploc) # all zero
- self.mc.VCHL(resloc, argloc, tmploc, l.itemsize_to_mask(size), 0b0001)
+ self.mc.VCHL(resloc, argloc, tmploc, l.itemsize_to_mask(size),
l.imm(0b0001))
flush_vec_cc(self, regalloc, c.VEQI, op.bytesize, resloc)
def emit_vec_float_eq(self, op, arglocs, regalloc):
@@ -198,7 +199,7 @@
size = sizeloc.value
if size == 8:
# bit 3 in last argument sets the condition code
- self.mc.VFCE(resloc, loc0, loc1, 3, 0, 1)
+ self.mc.VFCE(resloc, loc0, loc1, l.imm(3), l.imm(0), l.imm(1))
else:
not_implemented("[zarch/assembler] float == for size %d" % size)
flush_vec_cc(self, regalloc, c.VEQI, op.bytesize, resloc)
@@ -213,7 +214,7 @@
size = sizeloc.value
if size == 8:
# bit 3 in last argument sets the condition code
- self.mc.VFCE(resloc, loc0, loc1, 3, 0, 1)
+ self.mc.VFCE(resloc, loc0, loc1, l.imm(3), l.imm(0), l.imm(1))
self.mc.VNO(resloc, resloc, resloc)
else:
not_implemented("[zarch/assembler] float != for size %d" % size)
@@ -221,27 +222,27 @@
def emit_vec_cast_int_to_float(self, op, arglocs, regalloc):
resloc, loc0 = arglocs
- self.mc.VCDG(resloc, loc0, 3, 4, m.RND_TOZERO.value)
+ self.mc.VCDG(resloc, loc0, l.imm(3), l.imm(4), m.RND_TOZERO)
def emit_vec_int_eq(self, op, arglocs, regalloc):
assert isinstance(op, VectorOp)
resloc, loc0, loc1, sizeloc = arglocs
size = sizeloc.value
- self.mc.VCEQ(resloc, loc0, loc1, l.itemsize_to_mask(size), 1)
+ self.mc.VCEQ(resloc, loc0, loc1, l.itemsize_to_mask(size), l.imm(1))
flush_vec_cc(self, regalloc, c.VEQI, op.bytesize, resloc)
def emit_vec_int_ne(self, op, arglocs, regalloc):
assert isinstance(op, VectorOp)
resloc, loc0, loc1, sizeloc = arglocs
size = sizeloc.value
- self.mc.VCEQ(resloc, loc0, loc1, l.itemsize_to_mask(size), 1)
+ self.mc.VCEQ(resloc, loc0, loc1, l.itemsize_to_mask(size), l.imm(1))
self.mc.VNO(resloc, resloc, resloc)
- flush_vec_cc(self, regalloc, c.VNEI, op.bytesize, res)
+ flush_vec_cc(self, regalloc, c.VNEI, op.bytesize, resloc)
def emit_vec_cast_float_to_int(self, op, arglocs, regalloc):
resloc, loc0 = arglocs
# 4 => bit 1 from the MSB: XxC
- self.mc.VCGD(resloc, loc0, 3, 4, m.RND_TOZERO.value)
+ self.mc.VCGD(resloc, loc0, l.imm(3), l.imm(4), m.RND_TOZERO)
def emit_vec_expand_i(self, op, arglocs, regalloc):
assert isinstance(op, VectorOp)
@@ -267,10 +268,10 @@
if arg.type == FLOAT:
self.mc.VPDI(targetloc, accumloc, accumloc, permi(1,0))
if op == '+':
- self.mc.VFA(targetloc, targetloc, accumloc, 3, 0b1000, 0)
+ self.mc.VFA(targetloc, targetloc, accumloc, l.imm3,
l.imm(0b1000), l.imm(0))
return
elif op == '*':
- self.mc.VFM(targetloc, targetloc, accumloc, 3, 0b1000, 0)
+ self.mc.VFM(targetloc, targetloc, accumloc, l.imm3,
l.imm(0b1000), l.imm(0))
return
else:
assert arg.type == INT
@@ -314,7 +315,7 @@
# load from sourceloc into GP reg and store back into resloc
self.mc.VLGV(r.SCRATCH, sourceloc, sindex,
l.itemsize_to_mask(size))
rindex = l.addr(j + residx)
- self.mc.VLVG(resloc, sourceloc, rindex,
l.itemsize_to_mask(size))
+ self.mc.VLVG(resloc, r.SCRATCH, rindex,
l.itemsize_to_mask(size))
emit_vec_unpack_i = emit_vec_pack_i
@@ -510,14 +511,16 @@
arg = op.getarg(0)
if arg.is_vector():
srcloc = self.ensure_vector_reg(arg)
+ assert isinstance(arg, VectorOp)
+ size = arg.bytesize
else:
# unpack
- srcloc = self.ensure_reg(arg0)
+ srcloc = self.ensure_reg(arg)
+ size = WORD
if op.is_vector():
resloc = self.force_allocate_vector_reg(op)
else:
resloc = self.force_allocate_reg(op)
- size = arg.bytesize
return [resloc, srcloc, srcloc, imm(0), imm(index.value),
imm(count.value), imm(size)]
def prepare_vec_pack_f(self, op):
diff --git a/rpython/translator/platform/arch/s390x.py
b/rpython/translator/platform/arch/s390x.py
--- a/rpython/translator/platform/arch/s390x.py
+++ b/rpython/translator/platform/arch/s390x.py
@@ -40,15 +40,18 @@
def s390x_detect_vx():
with open("/proc/cpuinfo", "rb") as fd:
- lines = fd.read().splitlines()
- for line in lines:
- if line.startswith("features"):
- colonidx = line.find(':')
- split = line[colonidx+1:].strip().split(' ')
- if 'vx' in split:
- return True
- break
-
+ content = fd.read()
+ start = content.find("features", 0)
+ if start >= 0:
+ after_colon = content.find(":", start)
+ if after_colon < 0:
+ return False
+ newline = content.find("\n", after_colon)
+ if newline < 0:
+ return False
+ split = content[after_colon+1:newline].strip().split(' ')
+ if 'vx' in split:
+ return True
return False
def s390x_cpu_revision():
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