Author: Carl Friedrich Bolz-Tereick <cfb...@gmx.de>
Branch: regalloc-playground
Changeset: r92307:5c1a449086cd
Date: 2017-09-03 08:57 +0200
http://bitbucket.org/pypy/pypy/changeset/5c1a449086cd/
Log: test coalescing
diff --git a/rpython/jit/backend/x86/reghint.py
b/rpython/jit/backend/x86/reghint.py
--- a/rpython/jit/backend/x86/reghint.py
+++ b/rpython/jit/backend/x86/reghint.py
@@ -37,12 +37,10 @@
# For symmetrical operations, if 'y' is already in a register
# and won't be used after the current operation finishes,
# then swap the role of 'x' and 'y'
- if self.longevity[x].last_usage > position:
- if self.longevity[y].last_usage == position:
- x, y = y, x
- self.longevity.try_use_same_register(y, op)
- else:
- self.longevity.try_use_same_register(x, op)
+ if (self.longevity[x].last_usage > position and
+ self.longevity[y].last_usage == position):
+ x, y = y, x
+ self.longevity.try_use_same_register(x, op)
def _consider_binop(self, op, position):
self._consider_binop_part(op, position)
@@ -159,7 +157,6 @@
return None
def hint(self, position, args, argtypes, save_all_regs):
- import pdb; pdb.set_trace()
hinted_xmm = []
hinted_gpr = []
for i in range(len(args)):
diff --git a/rpython/jit/backend/x86/test/test_regalloc.py
b/rpython/jit/backend/x86/test/test_regalloc.py
--- a/rpython/jit/backend/x86/test/test_regalloc.py
+++ b/rpython/jit/backend/x86/test/test_regalloc.py
@@ -1,4 +1,6 @@
-""" annoying integration tests for register allocation in the x86 backend """
+""" explicit integration tests for register allocation in the x86 backend """
+
+import pytest
from rpython.jit.backend.llsupport.test import test_regalloc_integration
from rpython.jit.backend.x86.assembler import Assembler386
@@ -29,7 +31,6 @@
return Assembler386.mov(self, from_loc, to_loc)
def regalloc_mov(self, from_loc, to_loc):
- import pdb; pdb.set_trace()
self._log("mov", from_loc, to_loc)
return Assembler386.mov(self, from_loc, to_loc)
@@ -56,6 +57,10 @@
def setup_method(self, meth):
self.cpu.assembler._instr_log = self.log = []
+ def teardown_method(self, meth):
+ for l in self.log:
+ print l
+
def test_call_use_correct_regs(self):
ops = '''
[i0, i1, i2, i3]
@@ -68,5 +73,38 @@
'''
self.interpret(ops, [5, 6, 7, 8])
# two moves are needed from the stack frame to registers for arguments
- # i0 and i1 one for the result to the stack
+ # i0 and i1, one for the result to the stack
assert len([entry for entry in self.log if entry.name == "mov"]) == 3
+
+ def test_coalescing(self):
+ ops = '''
+ [i0, i1, i2, i3]
+ i7 = int_add(i0, i1)
+ i8 = int_add(i7, i3)
+ i9 = call_i(ConstClass(f1ptr), i8, descr=f1_calldescr)
+ i10 = int_is_true(i9)
+ guard_true(i10) []
+ finish(i9)
+ '''
+ self.interpret(ops, [5, 6, 7, 8])
+ # coalescing makes sure that i0 (and thus i71) lands in edi
+ assert len([entry for entry in self.log if entry.name == "mov"]) == 2
+
+ @pytest.mark.skip("later")
+ def test_binop_dont_swap_unnecessarily(self):
+ ops = '''
+ [i0, i1, i2, i3]
+ i7 = int_add(i0, i1)
+ i8 = int_add(i2, 13)
+ i9 = int_add(i7, i8)
+ i10 = int_is_true(i9)
+ guard_true(i10) []
+ finish(i9)
+ '''
+ self.interpret(ops, [5, 6, 7, 8])
+ add1 = self.log[2]
+ op = self.log[5]
+ assert op.name == "op"
+ # make sure that the arguments of the third op are not swapped (since
+ # that would break coalescing between i7 and i9
+ assert op.args[1][0] is add1.args[-1]
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