Author: Carl Friedrich Bolz-Tereick <[email protected]>
Branch: regalloc-playground
Changeset: r92323:494789502df8
Date: 2017-09-03 11:55 +0200
http://bitbucket.org/pypy/pypy/changeset/494789502df8/
Log: fix a bug with consta arguments
diff --git a/rpython/jit/backend/x86/regalloc.py
b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -512,11 +512,12 @@
# and if x lives longer than the current operation while y dies, then
# swap the role of 'x' and 'y'
if (symm and not isinstance(xloc, RegLoc) and
- isinstance(argloc, RegLoc) and
- self.rm.longevity[x].last_usage > self.rm.position and
- self.longevity[y].last_usage == self.rm.position):
- x, y = y, x
- argloc = self.loc(y)
+ isinstance(argloc, RegLoc)):
+ if ((x not in self.rm.longevity or
+ self.rm.longevity[x].last_usage > self.rm.position) and
+ self.rm.longevity[y].last_usage == self.rm.position):
+ x, y = y, x
+ argloc = self.loc(y)
#
args = op.getarglist()
loc = self.rm.force_result_in_reg(op, x, args)
@@ -613,7 +614,6 @@
vx = op.getarg(0)
vy = op.getarg(1)
arglocs = [self.loc(vx), self.loc(vy)]
- args = op.getarglist()
if (vx in self.rm.reg_bindings or vy in self.rm.reg_bindings or
isinstance(vx, Const) or isinstance(vy, Const)):
pass
diff --git a/rpython/jit/backend/x86/reghint.py
b/rpython/jit/backend/x86/reghint.py
--- a/rpython/jit/backend/x86/reghint.py
+++ b/rpython/jit/backend/x86/reghint.py
@@ -38,8 +38,10 @@
# For symmetrical operations, if y won't be used after the current
# operation finishes, but x will be, then swap the role of 'x' and 'y'
- if (self.longevity[x].last_usage > position and
- self.longevity[y].last_usage == position):
+ if (symm and isinstance(x, ConstInt) or (
+ not isinstance(y, ConstInt) and
+ self.longevity[x].last_usage > position and
+ self.longevity[y].last_usage == position)):
x, y = y, x
self.longevity.try_use_same_register(x, op)
@@ -77,6 +79,12 @@
consider_int_rshift = consider_int_lshift
consider_uint_rshift = consider_int_lshift
+ def consider_uint_mul_high(self, op, position):
+ # could do a lot more, but I suspect not worth it
+ # just block eax and edx
+ self.longevity.fixed_register(position, eax)
+ self.longevity.fixed_register(position, edx)
+
def Xconsider_call_malloc_nursery(self, op, position):
self.longevity.fixed_register(position, ecx, op)
self.longevity.fixed_register(position, edx)
@@ -108,7 +116,8 @@
assert effectinfo is not None
oopspecindex = effectinfo.oopspecindex
if oopspecindex != EffectInfo.OS_NONE:
- raise NotImplementedError
+ # XXX safe default: do nothing
+ return
self._consider_call(op, position)
consider_call_i = _consider_real_call
diff --git a/rpython/jit/backend/x86/test/test_regalloc.py
b/rpython/jit/backend/x86/test/test_regalloc.py
--- a/rpython/jit/backend/x86/test/test_regalloc.py
+++ b/rpython/jit/backend/x86/test/test_regalloc.py
@@ -72,6 +72,15 @@
self.interpret(ops, [5, 6, 7, 8])
assert len([entry for entry in self.log if entry.args[0] ==
"int_add"]) == 1
+ def test_bug_const(self):
+ ops = '''
+ [i0, i1, i2, i3]
+ i9 = int_add(1, i3)
+ finish(i9)
+ '''
+ # does not crash
+ self.interpret(ops, [5, 6, 7, 8])
+ assert len([entry for entry in self.log if entry.args[0] ==
"int_add"]) == 1
def test_call_use_correct_regs(self):
ops = '''
@@ -161,5 +170,5 @@
op = self.log[5]
assert op.name == "op"
# make sure that the arguments of the third op are not swapped (since
- # that would break coalescing between i7 and i9
+ # that would break coalescing between i7 and i9)
assert op.args[1][0] is add1.args[-1]
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