Author: Maciej Fijalkowski <[email protected]>
Branch: arm64
Changeset: r96489:27c1f4063137
Date: 2019-04-12 12:45 +0000
http://bitbucket.org/pypy/pypy/changeset/27c1f4063137/
Log: implement int ops
diff --git a/rpython/jit/backend/aarch64/codebuilder.py
b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -114,6 +114,11 @@
base = 0b11001011001
self.write32((base << 21) | (rm << 16) | (0b11 << 13) | (rn << 5) |
(rd))
+ def SUB_rr_shifted(self, rd, rn, rm, shift=0):
+ base = 0b11001011000
+ assert shift == 0
+ self.write32((base << 21) | (rm << 16) | (rn << 5) | rd)
+
def MUL_rr(self, rd, rn, rm):
base = 0b10011011000
self.write32((base << 21) | (rm << 16) | (0b11111 << 10) | (rn << 5) |
rd)
@@ -142,6 +147,10 @@
base = 0b11001010000
self.write32((base << 21) | (rm << 16) | (rn << 5) | rd)
+ def MVN_rr(self, rd, rm):
+ base = 0b10101010001
+ self.write32((base << 21) | (rm << 16) | (0b11111 << 5)| rd)
+
def CMP_rr(self, rn, rm):
base = 0b11101011000
self.write32((base << 21) | (rm << 16) | (rn << 5) | 0b11111)
diff --git a/rpython/jit/backend/aarch64/opassembler.py
b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -12,10 +12,7 @@
def emit_op(self, op, arglocs):
l0, l1, res = arglocs
- if l1.is_imm():
- self.mc.CMP_ri(l0.value, l1.getint())
- else:
- self.mc.CMP_rr(l0.value, l1.value)
+ self.emit_int_comp_op(op, l0, l1)
self.mc.CSET_r_flag(res.value, c.get_opposite_of(flag))
emit_op.__name__ = name
return emit_op
@@ -88,24 +85,22 @@
l0, l1, res = arglocs
self.mc.UMULH_rr(res.value, l0.value, l1.value)
- def emit_int_comp_op(self, op, arglocs):
- l0, l1 = arglocs
-
+ def emit_int_comp_op(self, op, l0, l1):
if l1.is_imm():
self.mc.CMP_ri(l0.value, l1.getint())
else:
self.mc.CMP_rr(l0.value, l1.value)
def emit_comp_op_int_lt(self, op, arglocs):
- self.emit_int_comp_op(op, arglocs)
+ self.emit_int_comp_op(op, arglocs[0], arglocs[1])
return c.LT
def emit_comp_op_int_le(self, op, arglocs):
- self.emit_int_comp_op(op, arglocs)
+ self.emit_int_comp_op(op, arglocs[0], arglocs[1])
return c.LE
def emit_comp_op_int_eq(self, op, arglocs):
- self.emit_int_comp_op(op, arglocs)
+ self.emit_int_comp_op(op, arglocs[0], arglocs[1])
return c.EQ
emit_op_int_lt = gen_comp_op('emit_op_int_lt', c.LT)
@@ -115,6 +110,31 @@
emit_op_int_eq = gen_comp_op('emit_op_int_eq', c.EQ)
emit_op_int_ne = gen_comp_op('emit_op_int_ne', c.NE)
+ emit_op_uint_lt = gen_comp_op('emit_op_uint_lt', c.LO)
+ emit_op_uint_gt = gen_comp_op('emit_op_uint_gt', c.HI)
+ emit_op_uint_le = gen_comp_op('emit_op_uint_le', c.LS)
+ emit_op_uint_ge = gen_comp_op('emit_op_uint_ge', c.HS)
+
+ def emit_op_int_is_true(self, op, arglocs):
+ reg, res = arglocs
+
+ self.mc.CMP_ri(reg.value, 0)
+ self.mc.CSET_r_flag(res.value, c.EQ)
+
+ def emit_op_int_is_zero(self, op, arglocs):
+ reg, res = arglocs
+
+ self.mc.CMP_ri(reg.value, 0)
+ self.mc.CSET_r_flag(res.value, c.NE)
+
+ def emit_op_int_neg(self, op, arglocs):
+ reg, res = arglocs
+ self.mc.SUB_rr_shifted(res.value, r.xzr.value, reg.value)
+
+ def emit_op_int_invert(self, op, arglocs):
+ reg, res = arglocs
+ self.mc.MVN_rr(res.value, reg.value)
+
def emit_op_increment_debug_counter(self, op, arglocs):
return # XXXX
base_loc, value_loc = arglocs
diff --git a/rpython/jit/backend/aarch64/regalloc.py
b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -385,6 +385,23 @@
prepare_op_int_ge = prepare_op_int_le
prepare_op_int_eq = prepare_op_int_le
prepare_op_int_ne = prepare_op_int_le
+ prepare_op_uint_lt = prepare_op_int_le
+ prepare_op_uint_le = prepare_op_int_le
+ prepare_op_uint_gt = prepare_op_int_le
+ prepare_op_uint_ge = prepare_op_int_le
+
+ def prepare_unary(self, op):
+ a0 = op.getarg(0)
+ assert not isinstance(a0, Const)
+ reg = self.make_sure_var_in_reg(a0)
+ self.possibly_free_vars_for_op(op)
+ res = self.force_allocate_reg(op)
+ return [reg, res]
+
+ prepare_op_int_is_true = prepare_unary
+ prepare_op_int_is_zero = prepare_unary
+ prepare_op_int_neg = prepare_unary
+ prepare_op_int_invert = prepare_unary
def prepare_op_label(self, op):
descr = op.getdescr()
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