Author: fijal Branch: arm64 Changeset: r96530:1fe592cd9f4d Date: 2019-04-22 11:17 +0200 http://bitbucket.org/pypy/pypy/changeset/1fe592cd9f4d/
Log: LSL_ri & ASR_ri diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py --- a/rpython/jit/backend/aarch64/codebuilder.py +++ b/rpython/jit/backend/aarch64/codebuilder.py @@ -10,6 +10,14 @@ PC_OFFSET = 0 # XXX class AbstractAarch64Builder(object): + # just copied some values from https://gist.github.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a + immr_imms = { + 32: (0b111011, 0b000000), + 56: (0b111101, 0b000010), + 48: (0b111100, 0b000001), + 16: (0b111100, 0b000000), + } + def write32(self, word): self.writechar(chr(word & 0xFF)) self.writechar(chr((word >> 8) & 0xFF)) @@ -135,10 +143,20 @@ base = 0b10011010110 self.write32((base << 21) | (rm << 16) | (0b001000 << 10) | (rn << 5) | rd) + def LSL_ri(self, rd, rn, shift): + immr, imms = self.immr_imms[shift] + base = 0b1101001101 + self.write32((base << 22) | (immr << 16) | (imms << 10) | (rn << 5) | rd) + def ASR_rr(self, rd, rn, rm): base = 0b10011010110 self.write32((base << 21) | (rm << 16) | (0b001010 << 10) | (rn << 5) | rd) + def ASR_ri(self, rd, rn, shift): + immr, imms = self.immr_imms[shift] + base = 0b1001001101 + self.write32((base << 22) | (immr << 16) | (imms << 10) | (rn << 5) | rd) + def LSR_rr(self, rd, rn, rm): base = 0b10011010110 self.write32((base << 21) | (rm << 16) | (0b001001 << 10) | (rn << 5) | rd) _______________________________________________ pypy-commit mailing list pypy-commit@python.org https://mail.python.org/mailman/listinfo/pypy-commit
