Author: fijal
Branch: arm64
Changeset: r96824:1f31b1f9873c
Date: 2019-06-18 17:23 +0200
http://bitbucket.org/pypy/pypy/changeset/1f31b1f9873c/
Log: more floats
diff --git a/rpython/jit/backend/aarch64/codebuilder.py
b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -30,6 +30,10 @@
assert 0 <= offset < 32768
self.write32((base << 22) | ((offset >> 3) << 10) | (rn << 5) | rt)
+ def STR_dd(self, rt, rn, rm):
+ base = 0b11111100001
+ self.write32((base << 21) | (rm << 16) | (0b011010 << 10) | (rn << 5)
| rt)
+
def STP_rr_preindex(self, reg1, reg2, rn, offset):
base = 0b1010100110
assert -512 <= offset < 512
@@ -122,6 +126,10 @@
base = 0b1111110101
self.write32((base << 22) | (offset >> 3 << 10) | (rn << 5) | rt)
+ def LDR_dr(self, rt, rn, rm):
+ base = 0b11111100011
+ self.write32((base << 21) | (rm << 16) | (0b011010 << 10) | (rn << 5)
| rt)
+
def LDRB_ri(self, rt, rn, immed):
base = 0b0011100101
assert 0 <= immed <= 1<<12
diff --git a/rpython/jit/backend/aarch64/opassembler.py
b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -348,7 +348,8 @@
self.mc.STR_di(value_loc.value, base_loc.value,
ofs_loc.value)
else:
- xxx
+ self.mc.STR_dd(value_loc.value, base_loc.value,
+ ofs_loc.value)
return
if ofs_loc.is_imm():
self.mc.STR_ri(value_loc.value, base_loc.value,
@@ -489,17 +490,24 @@
def emit_op_guard_value(self, op, arglocs):
v0 = arglocs[0]
- assert v0.is_core_reg() # can be also a float reg, but later
v1 = arglocs[1]
- if v1.is_core_reg():
- loc = v1
- elif v1.is_imm():
- self.mc.gen_load_int(r.ip0.value, v1.value)
- loc = r.ip0
+ if v0.is_core_reg():
+ if v1.is_core_reg():
+ loc = v1
+ elif v1.is_imm():
+ self.mc.gen_load_int(r.ip0.value, v1.value)
+ loc = r.ip0
+ else:
+ assert v1.is_stack()
+ yyy
+ self.mc.CMP_rr(v0.value, loc.value)
else:
- assert v1.is_stack()
- yyy
- self.mc.CMP_rr(v0.value, loc.value)
+ assert v0.is_vfp_reg()
+ if v1.is_vfp_reg():
+ loc = v1
+ else:
+ xxx
+ self.mc.FCMP_dd(v0.value, loc.value)
self._emit_guard(op, c.EQ, arglocs[2:])
def emit_op_guard_class(self, op, arglocs):
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