Author: Maciej Fijalkowski <[email protected]>
Branch: arm64
Changeset: r96854:d11024632dda
Date: 2019-06-24 10:08 +0000
http://bitbucket.org/pypy/pypy/changeset/d11024632dda/
Log: a few more obscure operations
diff --git a/rpython/jit/backend/aarch64/codebuilder.py
b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -246,6 +246,18 @@
base = 0b1001111001100010
self.write32((base << 16) | (rn << 5) | rd)
+ def SXTB_rr(self, rd, rn):
+ base = 0b1001001101000000000111
+ self.write32((base << 10) | (rn << 5) | rd)
+
+ def SXTH_rr(self, rd, rn):
+ base = 0b1001001101000000001111
+ self.write32((base << 10) | (rn << 5) | rd)
+
+ def SXTW_rr(self, rd, rn):
+ base = 0b1001001101000000011111
+ self.write32((base << 10) | (rn << 5) | rd)
+
def FSQRT_dd(self, rd, rn):
base = 0b0001111001100001110000
self.write32((base << 10) | (rn << 5) | rd)
diff --git a/rpython/jit/backend/aarch64/opassembler.py
b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -228,6 +228,26 @@
reg, res = arglocs
self.mc.MVN_rr(res.value, reg.value)
+ def emit_op_int_force_ge_zero(self, op, arglocs):
+ arg, res = arglocs
+ self.mc.MOVZ_r_u16(res.value, 0, 0)
+ self.mc.CMP_ri(arg.value, 0)
+ self.mc.B_ofs_cond(8, c.LT) # jump over the next instruction
+ self.mc.MOV_rr(res.value, arg.value)
+ # jump here
+
+ def emit_op_int_signext(self, op, arglocs):
+ arg, numbytes, res = arglocs
+ assert numbytes.is_imm()
+ if numbytes.value == 1:
+ self.mc.SXTB_rr(res.value, arg.value)
+ elif numbytes.value == 2:
+ self.mc.SXTH_rr(res.value, arg.value)
+ elif numbytes.value == 4:
+ self.mc.SXTW_rr(res.value, arg.value)
+ else:
+ raise AssertionError("bad number of bytes")
+
def emit_op_increment_debug_counter(self, op, arglocs):
return # XXXX
base_loc, value_loc = arglocs
diff --git a/rpython/jit/backend/aarch64/regalloc.py
b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -371,6 +371,17 @@
def prepare_comp_op_int_mul_ovf(self, op, res_in_cc):
return self.prepare_op_int_mul(op)
+ def prepare_op_int_force_ge_zero(self, op):
+ argloc = self.make_sure_var_in_reg(op.getarg(0))
+ resloc = self.force_allocate_reg(op, [op.getarg(0)])
+ return [argloc, resloc]
+
+ def prepare_op_int_signext(self, op):
+ argloc = self.make_sure_var_in_reg(op.getarg(0))
+ numbytes = op.getarg(1).getint()
+ resloc = self.force_allocate_reg(op)
+ return [argloc, imm(numbytes), resloc]
+
# some of those have forms of imm that they accept, but they're rather
# obscure. Can be future optimization
prepare_op_int_and = prepare_op_int_mul
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