Author: fijal
Branch: arm64
Changeset: r96903:d841bd0c34b4
Date: 2019-07-01 17:33 +0200
http://bitbucket.org/pypy/pypy/changeset/d841bd0c34b4/
Log: one missing one
diff --git a/rpython/jit/backend/aarch64/callbuilder.py
b/rpython/jit/backend/aarch64/callbuilder.py
--- a/rpython/jit/backend/aarch64/callbuilder.py
+++ b/rpython/jit/backend/aarch64/callbuilder.py
@@ -143,7 +143,7 @@
if gcrootmap:
rst = gcrootmap.get_root_stack_top_addr()
self.mc.gen_load_int(r.x19.value, rst)
- self.mc.LDR_ri(r.x20.value, r.x19.value)
+ self.mc.LDR_ri(r.x20.value, r.x19.value, 0)
# change 'rpy_fastgil' to 0 (it should be non-zero right now)
self.mc.DMB()
@@ -227,7 +227,7 @@
# thread. So here we check if the shadowstack pointer
# is still the same as before we released the GIL (saved
# in 'x20'), and if not, we fall back to 'reacqgil_addr'.
- self.mc.LDR_ri(r.ip0.value, r.x19.value)
+ self.mc.LDR_ri(r.ip0.value, r.x19.value, 0)
self.mc.CMP_rr(r.ip0.value, r.x20.value)
XXX
b1_location = self.mc.currpos()
_______________________________________________
pypy-commit mailing list
[email protected]
https://mail.python.org/mailman/listinfo/pypy-commit
