Author: fijal
Branch: arm64
Changeset: r96905:9581673169cb
Date: 2019-07-01 17:40 +0200
http://bitbucket.org/pypy/pypy/changeset/9581673169cb/
Log: name fixes
diff --git a/rpython/jit/backend/aarch64/assembler.py
b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -776,7 +776,7 @@
if kind == rewrite.FLAG_ARRAY:
self.mc.gen_load_int(r.x0.value, arraydescr.tid)
self.regalloc_mov(lengthloc, r.x1)
- self.gen_load_int(r.ip0.value, imm(itemsize))
+ self.mc.gen_load_int(r.ip0.value, itemsize)
addr = self.malloc_slowpath_varsize
else:
if kind == rewrite.FLAG_STR:
diff --git a/rpython/jit/backend/aarch64/codebuilder.py
b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -364,7 +364,7 @@
base = 0b10101010001
self.write32((base << 21) | (rm << 16) | (0b11111 << 5)| rd)
- def MVN_rr_shift(self, rd, rm, shift=0, shifttype=0): # defaults to LSL
+ def MVN_rr_shifted(self, rd, rm, shift=0, shifttype=0): # defaults to LSL
base = 0b10101010
assert 0 <= shift < 64
self.write32((base << 24) | (shifttype << 22) | (1 << 21) |
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