Author: fijal
Branch: arm64
Changeset: r96909:b16bba1b07a5
Date: 2019-07-01 18:16 +0200
http://bitbucket.org/pypy/pypy/changeset/b16bba1b07a5/
Log: typo
diff --git a/rpython/jit/backend/aarch64/assembler.py
b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -888,8 +888,8 @@
rst = gcrootmap.get_root_stack_top_addr()
mc.gen_load_int(r.ip0.value, rst)
self.load_reg(mc, r.ip0, r.ip0)
- mc.SUB_ri(r.ip0, r.ip0, WORD)
- mc.LDR_ri(r.fp, r.ip0, 0)
+ mc.SUB_ri(r.ip0.value, r.ip0.value, WORD)
+ mc.LDR_ri(r.fp.value, r.ip0.value, 0)
wbdescr = self.cpu.gc_ll_descr.write_barrier_descr
if gcrootmap and wbdescr:
# frame never uses card marking, so we enforce this is not
_______________________________________________
pypy-commit mailing list
[email protected]
https://mail.python.org/mailman/listinfo/pypy-commit
