Author: fijal
Branch: arm64
Changeset: r96912:371da80e47bf
Date: 2019-07-02 09:54 +0200
http://bitbucket.org/pypy/pypy/changeset/371da80e47bf/
Log: missing stack adjustment
diff --git a/rpython/jit/backend/aarch64/assembler.py
b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -382,6 +382,8 @@
assert exc0 is not None
assert exc1 is not None
+ mc.ADD_ri(r.sp.value, r.sp.value, (len(r.caller_resp) + 2 +
len(r.caller_vfp_resp)) * WORD)
+
#
if withcards:
# A final TEST8 before the RET, for the caller. Careful to
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