Author: fijal
Branch: arm64
Changeset: r96925:8c7dd5b87a48
Date: 2019-07-02 18:25 +0200
http://bitbucket.org/pypy/pypy/changeset/8c7dd5b87a48/
Log: bah
diff --git a/rpython/jit/backend/aarch64/regalloc.py
b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -477,7 +477,7 @@
def prepare_two_regs_op(self, op):
loc1 = self.make_sure_var_in_reg(op.getarg(0))
- loc2 = self.make_sure_var_in_reg(op.getarg(1))
+ loc2 = self.make_sure_var_in_reg(op.getarg(1), op.getarglist())
self.possibly_free_vars_for_op(op)
self.free_temp_vars()
res = self.force_allocate_reg(op)
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